CDK2000 Cirrus Logic, Inc., CDK2000 Datasheet - Page 15

• Manufacturer Part Number: CDK2000
• Description: Fractional-n Clock Multiplier with Internal LCO
• Manufacturer: Cirrus Logic, Inc.

DS844F1
5.5
PLL Clock Output
The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer.
The driver can be set to high-impedance with the M2 pin when the M2Config[1:0] global parameter is set to
either 000 or 010. The output from the PLL automatically drives a static low condition while the PLL is un-
locked (when the clock may be unreliable). This feature can be disabled by setting the ClkOutUnl global
parameter, however the state CLK_OUT may then be unreliable during an unlock condition.
Referenced Control
ClkOutUnl..............................“Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 20
ClkOutDis
M2Config[2:0]........................“M2 Pin Configuration (M2Config[2:0])” on page 21
PLL Output
..............................“M2 Configured as Output Disable” on page 17
0
2:1 Mux
0
1
ClkOutUnl
Parameter Definition
Figure 11. PLL Clock Output Options
PLL Locked/Unlocked
2:1 Mux
0
1
PLL Clock Output
PLLClkOut
M2Config[1:0] = 000, 010
M2 pin with
PLL Clock Output Pin
(CLK_OUT)
CS2300-OTP
15