MAX1717 Maxim, MAX1717 Datasheet - Page 30

• Manufacturer Part Number: MAX1717
• Description: Dynamically Adjustable / Synchronous Step-Down Controller for Notebook CPUs
• Manufacturer: Maxim

Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
The two-stage approach allows flexible placement due
to smaller circuit size and reduced local power dissipa-
tion. The power supply can be placed closer to the
CPU for better regulation and lower I
board traces. Although the two-stage design has worse
transient response than the single stage, this can be
offset by the use of a voltage-positioned converter.
Ceramic capacitors have advantages and disadvan-
tages. They have ultra-low ESR and are noncom-
bustible, relatively small, and nonpolarized. They are
also expensive and brittle, and their ultra-low ESR char-
acteristic can result in excessively high ESR zero fre-
quencies (affecting stability in nonvoltage-positioned
circuits). In addition, their relatively low capacitance
value can cause output overshoot when going abruptly
from full-load to no-load conditions, unless the inductor
value can be made small (high switching frequency), or
there are some bulk tantalum or electrolytic capacitors
in parallel to absorb the stored energy in the inductor.
In some cases, there may be no room for electrolytics,
creating a need for a DC-DC design that uses nothing
but ceramics.
The MAX1717 can take full advantage of the small size
and low ESR of ceramic output capacitors in a voltage-
positioned circuit. The addition of the positioning resistor
increases the ripple at FB, lowering the effective ESR
zero frequency of the ceramic output capacitor.
Output overshoot (V
output capacitance requirement (see Output Capacitor
Selection). Often the switching frequency is increased to
550kHz or 1000kHz, and the inductor value is reduced to
minimize the energy transferred from inductor to capacitor
during load-step recovery. The efficiency penalty for
operating at 550kHz is about 2% to 3% and about 5% at
1000kHz when compared to the 300kHz voltage-
positioned circuit, primarily due to the high-side MOSFET
switching losses.
Table 1 and the Typical Operating Characteristics
include two circuits using ceramic capacitors with
1000kHz switching frequencies. The efficiency of the
+5V input circuit (circuit 4) is substantially higher than
circuit 5, which accommodates the full battery voltage
range. Circuit 4 is an excellent choice for two-stage
conversion applications if the goal is to minimize size
and power dissipation near the CPU.
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
30
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PC Board Layout Guidelines
Ceramic Output Capacitor
SOAR
) determines the minimum
2
R losses from PC
Applications
switching power stage requires particular attention
(Figure 12). If possible, mount all of the power compo-
nents on the top side of the board with their ground ter-
minals flush against one another. Follow these
guidelines for good PC board layout:
1) Keep the high-current paths short, especially at the
2) All analog grounding is done to a separate solid cop-
3) Keep the power traces and load connections short.
4) LX and GND connections to Q2 for current limiting
5) When trade-offs in trace lengths must be made, it’s
6) Ensure the FB connection to the output is short and
7) Route high-speed switching nodes away from sensitive
1) Place the power components first, with ground termi-
ground terminals. This is essential for stable, jitter-
free operation.
per plane, which connects to the MAX1717 at the
GND pin. This includes the V
capacitors, the TIME resistor, as well as any other
resistor-dividers.
This is essential for high efficiency. The use of thick
copper PC boards (2oz vs. 1oz) can enhance full-
load efficiency by 1% or more. Correctly routing PC
board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single milliohm of excess trace resistance
causes a measurable efficiency penalty.
must be made using Kelvin sense connections to
guarantee the current-limit accuracy. With SO-8
MOSFETs, this is best done by routing power to the
MOSFETs from outside using the top copper layer,
while connecting GND and LX inside (underneath)
the SO-8 package.
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it’s better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-side
MOSFET or between the inductor and the output filter
capacitor.
direct. In voltage-positioned circuits, the FB connection
is at the junction of the inductor and the positioning
resistor.
analog areas (CC, REF, ILIM). Make all pin-strap
control input connections (SKP/SDN, ILIM, etc.) to ana-
log ground or V
nals adjacent (Q2 source, CIN-, COUT-, D1 anode).
If possible, make all these connections on the top
layer with wide, copper-filled areas.
CC
rather than power ground or V
Layout Procedure
CC
, REF, and CC
DD
.