MAX1717 Maxim, MAX1717 Datasheet - Page 27

• Manufacturer Part Number: MAX1717
• Description: Dynamically Adjustable / Synchronous Step-Down Controller for Notebook CPUs
• Manufacturer: Maxim

For maximum efficiency, choose a high-side MOSFET
(Q1) that has conduction losses equal to the switching
losses at the optimum battery voltage (15V). Check to
ensure that the conduction losses at minimum input
voltage don’t exceed the package thermal limits or violate
the overall thermal budget. Check to ensure that con-
duction losses plus switching losses at the maximum
input voltage don’t exceed the package ratings or vio-
late the overall thermal budget.
Choose a low-side MOSFET (Q2) that has the lowest
possible R
(i.e., one or two SO-8s, DPAK or D
ably priced. Ensure that the MAX1717 DL gate driver
can drive Q2; in other words, check that the dv/dt
caused by Q1 turning on does not pull up the Q2 gate
due to drain-to-gate capacitance, causing cross-con-
duction problems. Switching losses aren’t an issue for
the low-side MOSFET since it’s a zero-voltage switched
device when used in the buck topology.
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET, the worst-case
power dissipation due to resistance occurs at minimum
battery voltage:
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the R
power-dissipation limits often limits how small the MOS-
FET can be. Again, the optimum occurs when the
switching losses equal the conduction (R
es. High-side switching losses don’t usually become an
issue until the input is greater than approximately 15V.
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
CV
FET you’ve chosen for adequate R
voltages becomes extraordinarily hot when subjected
to V
Calculating the power dissipation in Q1 due to switch-
ing losses is difficult since it must allow for difficult
quantifying factors that influence the turn-on and turn-
off times. These factors include the internal gate resis-
tance, gate charge, threshold voltage, source induc-
tance, and PC board layout characteristics. The following
switching-loss calculation provides only a very rough
estimate and is no substitute for breadboard evalua-
2
ƒ
IN(MAX)
SW
PD Q
switching-loss equation. If the high-side MOS-
(
DS(ON)
, reconsider your choice of MOSFET.
1
Re
DS(ON)
sistive
Step-Down Controller for Notebook CPUs
, comes in a moderate-sized package
______________________________________________________________________________________
MOSFET Power Dissipation
)
=
required to stay within package
Dynamically Adjustable, Synchronous
V
V
OUT
IN
⋅
I
LOAD
2
DS(ON)
PAK), and is reason-
2
⋅
R
at low battery
DS ON
DS(ON)
(
)
) loss-
tion, preferably including verification using a thermo-
couple mounted on Q1:
where C
and I
(1A typ).
For the low-side MOSFET (Q2), the worst-case power
dissipation always occurs at maximum battery voltage:
The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than
I
the current limit and cause the fault latch to trip. To pro-
tect against this possibility, you can “overdesign” the
circuit to tolerate:
where I
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. This means that
the MOSFETs must be very well heatsinked. If short-cir-
cuit protection without overload protection is enough, a
normal I
nent stresses.
Choose a Schottky diode (D1) having a forward voltage
low enough to prevent the Q2 MOSFET body diode
from turning on during the dead time. As a general rule,
a diode having a DC current rating equal to 1/3 of the
load current is sufficient. This diode is optional and can
be removed if efficiency isn’t critical.
Powering new mobile processors requires new tech-
niques to reduce cost, size, and power dissipation.
Voltage positioning reduces the total number of output
capacitors to meet a given transient response require-
ment. Setting the no-load output voltage slightly higher
allows a larger step down when the output current sud-
denly increases, and regulating at the lower output volt-
age under load allows a larger step up when the output
current suddenly decreases. Allowing a larger step size
means that the output capacitance can be reduced
and the capacitor’s ESR can be increased.
LOAD(MAX)
PD Q Switching
(
GATE
I
LOAD
1
PD Q
LOAD
LIMIT(HIGH)
RSS
(
is the peak gate-drive source/sink current
= I
but are not quite high enough to exceed
2
is the reverse transfer capacitance of Q1
)
value can be used for calculating compo-
LIMIT(HIGH)
=



1
)
−
=
C
V
is the maximum valley current
IN MAX
V
RSS
OUT
(
Voltage Positioning and
Application Issues
+ (LIR / 2) · I
⋅
V
)
IN MAX



Effective Efficiency
(
I
LOAD
I
GATE
)
2
2
⋅
LOAD(MAX)
⋅
ƒ
R
SW
DS ON
(
⋅
I
LOAD
)
27