ATA8741 ATMEL Corporation, ATA8741 Datasheet - Page 50

• Manufacturer Part Number: ATA8741
• Manufacturer: ATMEL Corporation

15. Power Management and Sleep Modes
15.1
15.2
50
Sleep Modes
Idle Mode
ATA8741
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
Figure 14-1 on page 41
tribution. The figure is helpful in selecting an appropriate sleep mode.
different sleep modes and their wake up sources
Table 15-1.
Note:
To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic one and a
SLEEP instruction must be executed. The SM1..0 bits in the MCUCR Register select which
sleep mode (Idle, ADC Noise Reduction, Standby or Power-down) will be activated by the
SLEEP instruction. See
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing Analog Comparator, ADC, Timer/Counter, Watchdog, and the
interrupt system to continue operating. This sleep mode basically halts clk
allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required,
Sleep Mode
Idle
ADC Noise
Reduction
Power-down
Stand-by
1. For INT0, only level interrupt.
2. Only recommended with external crystal or resonator selected as clock source
(2)
Active Clock Domains and Wake-up Sources in the Different Sleep Modes
Active Clock Domains
presents the different clock systems in the ATtiny24/44/84, and their dis-
Table 15-2 on page 53
X
X
X
for a summary.
Oscillators
X
X
X
X
X
X
(1)
(1)
Wake-up Sources
X
X
X
Table 15-1
CPU
(1)
and clk
9140B–INDCO–07/09
X
X
FLASH
shows the
X
, while
X
X
X