ATA8741 ATMEL Corporation, ATA8741 Datasheet - Page 178

• Manufacturer Part Number: ATA8741
• Manufacturer: ATMEL Corporation

27.1.4
27.2
27.2.1
178
Register Description
ATA8741
Programming Time for Flash when Using SPM
SPMCSR – Store Program Memory Control and Status Register
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
2. Keep the AVR core in Power-down sleep mode during periods of low V
The calibrated RC Oscillator is used to time Flash accesses.
gramming time for Flash accesses from the CPU.
Table 27-1.
Note:
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Program memory operations.
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATtiny24/44/84 and always read as zero.
• Bit 4 – CTPB: Clear Temporary Page Buffer
If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be
cleared and the data will be lost.
• Bit 3 – RFLB: Read Fuse and Lock Bits
An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register,
will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destina-
tion register. See
• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock
cycles executes Page Write, with the data stored in the temporary buffer. The page address is
taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit
Bit
0x37 (0x57)
Read/Write
Initial Value
Flash write (Page Erase, Page Write, and
write Lock bits by SPM)
This can be done by enabling the internal Brown-out Detector (BOD) if the operating volt-
age matches the detection level. If not, an external low V
used. If a reset occurs while a write operation is in progress, the write operation will be
completed provided that the power supply voltage is sufficient.
vent the CPU from attempting to decode and execute instructions, effectively protecting
the SPMCSR Register and thus the Flash from unintentional writes.
1. The min and max programming times is per individual operation.
SPM Programming Time
Symbol
R
7
–
0
“EEPROM Write Prevents Writing to SPMCSR” on page 177
R
6
–
0
R
5
–
0
(1)
Min Programming Time
CTPB
R/W
4
0
3.7 ms
RFLB
R/W
3
0
CC
PGWRT
Table 27-1
reset protection circuit can be
R/W
2
0
Max Programming Time
PGERS
R/W
1
0
shows the typical pro-
CC
. This will pre-
4.5 ms
for details.
SPMEN
9140B–INDCO–07/09
R/W
0
0
SPMCSR