MAX1400 Maxim, MAX1400 Datasheet - Page 12

• Manufacturer Part Number: MAX1400
• Description: %V / 18-Bit / Low-Power / Multichannel / Oversampling Sigma-Delta ADC
• Manufacturer: Maxim

+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
The serial digital interface provides access to eight on-
chip registers (Figure 3). All serial-interface commands
begin with a write to the communications register
(COMM). On power-up, system reset, or interface reset,
the part expects a write to its communications register.
The COMM register access begins with a 0 start bit.
The COMM register R/W bit selects a read or write
operation, and the register select bits (RS2, RS1, RS0)
select the register to be addressed. Hold DIN high
when not writing to COMM or another register (Table 1).
The serial interface consists of five signals: CS, SCLK,
DIN, DOUT, and INT. Clock pulses on SCLK shift bits
into DIN and out of DOUT. INT provides an indication
that data is available. CS is a device chip-select input
as well as a clock polarity select input (Figure 4).
Using CS allows the SCLK, DIN, and DOUT signals to
be shared among several SPI-compatible devices.
When short on I/O pins, connect CS low and operate
the serial digital interface in CPOL = 1, CPHA = 1 mode
using SCLK, DIN, and DOUT. This 3-wire interface
mode is ideal for opto-isolated applications.
Furthermore, a microcontroller (such as a PIC16C54 or
80C51) can use a single bidirectional I/O pin for both
sending to DIN and receiving from DOUT (see
Applications Information ), because the MAX1400 drives
DOUT only during a read cycle.
Additionally, connecting the INT signal to a hardware
interrupt allows faster throughput and reliable, collision-
free data flow.
The MAX1400 features a mode where the raw modula-
tor data output is accessible. In this mode the DOUT
and INT functions are reassigned (see the Modulator
Data Output section).
Table 1. Control Register Addressing
12
RS2
0
0
0
0
1
1
1
1
______________________________________________________________________________________
RS1
0
0
1
1
0
0
1
1
RS0
0
1
0
1
0
1
0
1
Communications Register
Global Setup Register 1
Global Setup Register 2
Special Function Register
Transfer Function Register 1
Transfer Function Register 2
Transfer Function Register 3
Data Register
Serial Digital Interface
TARGET REGISTER
Figure 3. Register Summary
Figure 4. Serial-Interface Timing
(CPOL = 1)
(CPOL = 0)
*DOUT IS HIGH IMPEDANCE DURING THE WRITE CYCLE; DIN IS IGNORED
(DURING
DURING THE READ CYCLE.
(DURING
WRITE)*
READ)*
DIN
DOUT
SCLK
SCLK
DOUT
INT
DIN
CS
t
1
t
3
t
t
t
12
t
6
4
14
SPECIAL FUNCTION REGISTER
COMMUNICATIONS REGISTER
XFER FUNCTION REGISTER 1
XFER FUNCTION REGISTER 2
XFER FUNCTION REGISTER 3
GLOBAL SETUP REGISTER 1
GLOBAL SETUP REGISTER 2
DATA REGISTER D1–D0/CID
t
t
13
DATA REGISTER D17–D10
5
RS2
DATA REGISTER D9–D2
MSB D6
MSB D6
RS1
RS0
t
15
D5
D5
t
16
t
7
t
t
17
8
D4
D4
D3
D3
D2
D2
D1
D1
REGISTER
DECODER
SELECT
D0
D0
t
10
t
t
18
9
t
11