MAX1359B Maxim Integrated Products, MAX1359B Datasheet - Page 26

• Manufacturer Part Number: MAX1359B
• Description: Data-Acquisition System
• Manufacturer: Maxim Integrated Products

DataSheet.in
The output data rate for the digital filter corresponds
with the positioning of the first notch of the filter’s fre-
quency response. The notches of the SINC
repeated at multiples of the first notch frequency. The
SINC
100dB at these notches. For example, 50Hz is equal to
five times the first notch frequency and 60Hz is equal to
six times the first notch frequency.
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Figure 4. Filter Frequency Response
Figure 5. Linear-Regulator Block Diagram
26
DV
DD
______________________________________________________________________________________
4
filter provides an attenuation of better than
-120
-160
-200
-40
-80
LINEAR 1.65V VOLTAGE REGULATOR
LDOE
0
0
1.22V
20
OP
LDOE
40
FREQUENCY (Hz)
60
80
1.65V
100
120
4
filter are
REG
The MAX1359B incorporates a 10-bit force-sense DAC.
The DAC’s reference voltage sets the full-scale range.
Program the DACA_OP register using the serial inter-
face to set the output voltages of the DAC at OUTA.
Shorting FBA and OUTA configures the DAC in a unity-
gain setting. Connecting resistors in a voltage-divider
configuration between OUTA, FBA, and GND sets a dif-
ferent closed-loop gain for the output amplifier (see the
Applications Information section).
The DAC output amplifier typically settles to ±0.5 LSB
from a full-scale transition within 50µs (unity gain and
loaded with 10kΩ in parallel with 200pF). Loads of less
than 1kΩ may degrade performance. See the Typical
Operating Characteristics for the source-and-sink
capability of the DAC output.
The MAX1359B features a software-programmable
shutdown mode for the DAC (see the DACA_OP
Register section). DAC output OUTA goes high imped-
ance when powered down. The DAC is normally pow-
ered down at power-on reset.
The charge pump provides >3V at CPOUT with a maxi-
mum 10mA load. Enable the charge pump through the
PS_VMONS register. The charge pump is powered
from DV
the charge pump and linear regulator. The charge
pump is disabled at power-on reset.
Figure 6. Charge-Pump Block Diagram
REG
M32K
DD
. See Figures 5 and 6 for block diagrams of
CLOCK GENERATOR
NONOVERLAP
CPE
CHARGE-PUMP DOUBLER
Force-Sense DAC
Charge Pump
CPOUT
CF-
CF+