MAX1333 Maxim Integrated Products, MAX1333 Datasheet - Page 15

• Manufacturer Part Number: MAX1333
• Description: (MAX1332 / MAX1333) True-Differential 12-Bit ADCs
• Manufacturer: Maxim Integrated Products

Figure 4. Detailed Serial-Interface Timing
Figure 5. Interface Timing Sequence
modes, the input common-mode voltage can vary as
long as the voltage at any single analog input (V
V
ply rails (AV
As shown in
the analog input voltage within the region of the analog
power-supply rails (AV
input voltage to swing from AGND - 0.3V to AV
without damage. Input voltages beyond AGND - 0.3V
and AV
diodes. In this situation, limit the forward diode current to
50mA to avoid damaging the MAX1332/MAX1333.
Conversion-start and data-read operations are con-
trolled by the CNVST and SCLK digital inputs. CNVST
controls the state of the T/H as well as when a conver-
sion is initiated. CNVST also controls the power-down
mode of the device (see the Partial Power-Down (PPD)
AIN_N
) remains within 50mV of the analog power sup-
DD
AND HOLD STATE
CNVST
DOUT
INPUT TRACK
SCLK
CNVST
+ 0.3V forward bias the internal protection
DD
DOUT
ANALOG
SCLK
Figure 3, internal protection diodes confine
, AGND).
HIGH-Z
______________________________________________________________________________________
Serial Digital Interface
DD
t
SETUP
3Msps/2Msps, 5V/3V, 2-Channel, True-
, AGND) and allow the analog
1
t
CFDE
t
0
SETUP
Timing and Control
2
0
3
0
4
D11
t
DD
CP
5
D10
+ 0.3V
AIN_P
6
POWER- MODE SELECTION WINDOW
D9
t
HOLD
CONV
,
7
D8
Differential 12-Bit ADCs
t
DHOLD
and Full Power-Down (FPD) Mode section). SCLK
clocks data out of the serial interface and sets the con-
version speed. Figures 4 and 5 show timing diagrams
that outline the serial-interface operation.
On power-up, the MAX1332/MAX1333 enter full power-
down mode. The first rising edge of CNVST exits the full
power-down mode and the MAX1332/MAX1333 begin
acquiring the analog input. A CNVST falling edge initi-
ates a conversion sequence. The T/H stage holds the
input voltage; DOUT changes from high impedance to
logic low; and the ADC begins to convert at the first
SCLK rising edge. SCLK is used to drive the conver-
sion process, and it shifts data out of DOUT. SCLK
begins shifting out the data after the 4th rising edge of
SCLK. DOUT transitions t
edge and remains valid for t
edge. The 4th rising clock edge produces the MSB of
the conversion result at DOUT, and the MSB remains
valid t
8
D7
t
DOT
DHOLD
9
D6
10
D5
after the 5th rising edge of SCLK. Sixteen
11
D4
12
D3
t
HOLD
13
DOT
CONTINUOUS-CONVERSION
SELECTION WINDOW
Starting a Conversion
D2
DHOLD
t
CRDD
14
after each SCLK’s rising
D1
t
CSW
TRACK
t
ACQ
15
after the next rising
D0
16
0
15