MAX1333 Maxim Integrated Products, MAX1333 Datasheet - Page 13

• Manufacturer Part Number: MAX1333
• Description: (MAX1332 / MAX1333) True-Differential 12-Bit ADCs
• Manufacturer: Maxim Integrated Products

The MAX1332/MAX1333 use an input track and hold
(T/H) circuit along with a successive-approximation
register (SAR) to convert a differential analog input sig-
nal to a digital 12-bit output. The serial interface
requires only three digital lines (SCLK, CNVST, and
DOUT) and provides easy interfacing to microcon-
trollers (µCs) and DSPs.
block diagram for the MAX1332/MAX1333.
The MAX1332/MAX1333 accept two power supplies
that allow the digital noise to be isolated from sensitive
analog circuitry. For both the MAX1332 and MAX1333,
the digital power-supply input accepts a supply voltage
of +2.7V to +3.6V. However, the supply voltage range
for the analog power supply is different for each
device. The MAX1332 accepts a +4.75V to +5.25V
analog power supply, and the MAX1333 accepts
a +2.7V to +3.6V analog power supply. See the Layout,
Grounding, and Bypassing section for information on
how to isolate digital noise from the analog power input.
The MAX1332/MAX1333s’ analog power supply con-
sists of one AV
exposed paddle (EP). The digital power input consists
of one DV
the potential on both AGND inputs is the same.
Furthermore, ensure that the potential between AGND
and DGND is limited to ±0.3V. Ideally there should be
no potential difference between AGND and DGND.
There are no power sequencing issues between AV
and DV
insensitive to power-up sequencing.
The equivalent input circuit of Figure 3 shows the
MAX1332/MAX1333s’ input architecture, which is com-
posed of a T/H, a comparator, and a switched-capaci-
tor DAC. On power-up, the MAX1332/MAX1333 enter
full power-down mode. Drive CNVST high to exit full
power-down mode and to start acquiring the input. The
positive input capacitor is connected to AIN_P and the
negative input capacitor is connected to AIN_N. The
T/H enters its hold mode on the falling edge of CNVST
and the ADC starts converting the sampled difference
between the analog inputs. Once a conversion has
been initiated, the T/H enters acquisition mode for the
next conversion on the 13th falling edge of SCLK after
CNVST has been transitioned from high to low.
The time required for the T/H to acquire an input signal
is determined by how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
DD
DD
. The analog and digital power supplies are
True-Differential Analog Input T/H
input and one DGND input. Ensure that
DD
______________________________________________________________________________________
input, two AGND inputs, and the
Detailed Description
3Msps/2Msps, 5V/3V, 2-Channel, True-
Figure 2 shows the simplified
Power Supplies
DD
Differential 12-Bit ADCs
the acquisition time lengthens. The acquisition time,
t
acquired. It is calculated by the following equation:
where:
The constant k is the number of RC time constants
required so that the voltage on the internal sampling
capacitor reaches N-bit accuracy, i.e., so that the dif-
ference between the input voltage and the sampling
capacitor voltage is equal to 0.5 LSB. N = 12 for the
MAX1332/MAX1333.
R
resistance, C
log input capacitance, and R
impedance of the input signal. Note that t
less than 52µs for the MAX1332 and 78µs for the
MAX1333, and any source impedance below 160Ω does
not significantly affect the ADC’s AC performance.
The ADC’s input-tracking circuitry has a 5MHz small-
signal bandwidth, making it possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
Figure 2. Simplified Functional Diagram
ACQ
IN
AIN0N
AIN1N
AIN0P
AIN1P
REF
= 250Ω is the equivalent differential analog input
, is the minimum time needed for the signal to be
t
ACQ
IN
AND T/H
INPUT
MUX
MAX1333
MAX1332
= 14pF is the equivalent differential ana-
AGND
AV
≥ k x (R
DD
k
= ≈
12-BIT SAR
9
SOURCE
ADC
ln (
2 2
LOGIC AND
CONTROL
×
TIMING
SOURCE
+ R
N
DV
DGND
Input Bandwidth
OUTPUT
BUFFER
)
DD
IN
) x C
is the source
ACQ
IN
CNVST
SCLK
SHDN
CHSEL
BIP/UNI
is never
DOUT
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