MAX1284 Maxim, MAX1284 Datasheet - Page 8

• Manufacturer Part Number: MAX1284
• Description: 400ksps/300ksps / Single-Supply / Low-Power / Serial 12-Bit ADCs with Internal Reference
• Manufacturer: Maxim

The MAX1284/MAX1285 use an input T/H and succes-
sive-approximation register (SAR) circuitry to convert
an analog input signal to a digital 12-bit output. Figure
3 shows the MAX1284/MAX1285 in its simplest configu-
ration. The internal reference is trimmed to +2.5V. The
serial interface requires only three digital lines (SCLK,
CS, and DOUT) and provides an easy interface to
microprocessors (µPs).
The MAX1284/MAX1285 have two modes: normal and
shutdown. Pulling SHDN low shuts the device down and
reduces supply current to below 2µA (typ), while pulling
SHDN high puts the device into operational mode. Pulling
CS low initiates a conversion that is driven by SCLK. The
conversion result is available at DOUT in unipolar serial
format. The serial data stream consists of three zeros,
followed by the data bits (MSB first). All transitions on
DOUT occur 20ns after the rising edge of SCLK. Figures
8 and 9 show the interface timing information.
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
Figure 1. Load Circuits for DOUT Enable Time
8
Figure 2. Load Circuits for DOUT Disable Time
_______________________________________________________________________________________
a) High-Z to V
a) V
DOUT
DOUT
OH
to High-Z
OH
6k
and V
6k
OL
to V
Detailed Description
DGND
OH
DGND
Converter Operation
C
LOAD
C
LOAD
= 20pF
= 20pF
Figure 4 illustrates the sampling architecture of the
ADC’s comparator. The full-scale input voltage is set by
the internal reference (V
In track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
During acquisition, the analog input (AIN) charges
capacitor C
interval. At this instant, the T/H switches the input side
of C
resents a sample of the input, unbalancing node ZERO
at the comparator’s input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to 0 within the limits of 12-
bit resolution. This action is equivalent to transferring a
charge from C
DAC, which in turn forms a digital representation of the
analog input signal. At the conversion’s end, the input
b) V
HOLD
OL
DOUT
to High-Z
b) High-Z to V
to GND. The retained charge on C
HOLD
DOUT
HOLD
OL
. Bringing CS low, ends the acquisition
and V
V
DD
OH
6k
to the binary-weighted capacitive
C
to V
LOAD
DGND
REF
V
OL
DD
= 20pF
6k
= +2.5V).
C
LOAD
DGND
= 20pF
Analog Input
Track/Hold
HOLD
rep-