MAX1284 Maxim, MAX1284 Datasheet - Page 12

• Manufacturer Part Number: MAX1284
• Description: 400ksps/300ksps / Single-Supply / Low-Power / Serial 12-Bit ADCs with Internal Reference
• Manufacturer: Maxim

Data can be output in two bytes or continuously, as
shown in Figure 8. The bytes contain the result of the
conversion padded with three leading zeros and three
trailing zeros.
When using SPI or MICROWIRE, set CPOL = 0 and
CPHA = 0. Conversion begins with a CS falling edge.
DOUT goes low, indicating a conversion in progress. Two
consecutive 1-byte reads are required to get the full
twelve bits from the ADC. DOUT output data transitions
on SCLK’s rising edge and is clocked into the following
µP on the rising edge.
The first byte contains three leading zeros, and five bits of
conversion result. The second byte contains the remaining
seven bits and one trailing zero. See Figure 11 for con-
nections and Figure 12 for timing.
SCLK to DOUT valid timing characteristic. Data can be
clocked into the µP on SCLK rising edge.
3) Pull CS high at or after the 15th rising clock edge. If CS
4) With CS = high, wait the minimum specified time, t
CS must be held low until all data bits are clocked out.
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
12
Figure 10. Unipolar Transfer Function, Full Scale (FS) =
V
REF
remains low, trailing zeros are clocked out after the
LSB.
before initiating a new conversion by pulling CS low. If
a conversion is aborted by pulling CS high before the
conversion completes, wait for the minimum acquisition
time, t
______________________________________________________________________________________
11 111
11 110
11 101
00 011
00 010
00 001
00 000
- 1LSB, Zero Scale (ZS) = GND
OUTPUT CODE
ACQ
0
, before starting a new conversion.
1
INPUT VOLTAGE (LSBs)
2
3
FULL-SCALE
TRANSITION
SPI and MICROWIRE
FS - 3/2LSB
FS = V
1LSB = V
FS
REF
4096
REF
- 1LSB
CS,
Unlike SPI, which requires two 1-byte reads to acquire
the 12 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles necessary to clock in the
data. The MAX1284/MAX1285 require 15 clock cycles
from the µP to clock out the 12 bits of data. Figure 13
shows a transfer using CPOL = 0 and CPHA = 1. The
conversion result contains two zeros followed by the 12
bits of data in MSB-first formatted.
For best performance, use PC boards. Wire-wrap boards
are not recommended. Board layout should ensure that
digital and analog signal lines are separated from each
other. Do not run analog and digital (especially clock)
lines parallel to one another, or digital lines underneath
the ADC package.
Figure 11. Common Serial-Interface Connections to the
MAX1284/MAX1285
a) SPI
b) QSPI
c) MICROWIRE
Layout, Grounding, and Bypassing
MISO
MISO
SCK
SCK
I/O
CS
I/O
SS
SS
SK
SI
+3V TO +5V
+3V TO +5V
CS
SCLK
DOUT
CS
SCLK
DOUT
CS
SCLK
DOUT
MAX1284
MAX1285
MAX1284
MAX1285
MAX1284
MAX1285
QSPI