MAX1161 Maxim, MAX1161 Datasheet - Page 8

• Manufacturer Part Number: MAX1161
• Description: 10-Bit / 40Msps / TTL-Output ADC
• Manufacturer: Maxim

The MAX1161 is driven from a single-ended TTL input
(CLK). The CLK pulse width (t
between 10ns and 300ns to ensure proper operation of
the internal track/hold amplifier (Figure 1a). When oper-
ating the MAX1161 at sampling rates above 3Msps, it is
recommended that the clock input duty cycle be kept
at 50% to optimize performance (Figure 4). The analog
input signal is latched on the rising edge of CLK.
The clock input must be driven from fast TTL logic (VIH
≤ 4.5V, t
a high current source, use a 100Ω resistor (R5) in
series to limit current to approximately 45mA.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8
© 1997 Maxim Integrated Products
10-Bit, 40Msps, TTL-Output ADC
Table 2. Output Data Information
(Ø indicates the flickering bit between logic 0 and 1.)
Figure 4. SNR vs. Clock Duty Cycle
> +2V + 1/2LSB
___________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 [phone]
+2V - 1LSB
-2V + 1LSB
ANALOG
INPUT
< 2V
0.0V
RISE
59
57
55
53
51
49
47
45
43
<6ns). In the event the clock is driven from
25
DUTY CYCLE OF POSITIVE CLOCK PULSE (°C)
30
35 40
OVERRANGE
D10
45 50 55
t
pwH
DUTY CYCLE =
1
0
0
0
0
t
pwL
pwH
60 65 70 75
t
t
pwL
pwH
1 1 1 111 1111
1 1 1 111 111Ø
ØØ ØØØØ ØØØØ
00 0000 000Ø
00 0000 0000
Printed USA
OUTPUT CODE
) must be kept
Clock Input
D9–D0
The format of the output data (D0–D9) is straight binary
(Table 2). The outputs are latched on the rising edge of
CLK with a propagation delay typically at 14ns. There is
a one-clock-cycle latency between CLK and the valid
output data (Figure 1a).
The digital outputs’ rise and fall times are not symmetri-
cal. Typical propagation delay is 14ns for the rise time
and 6ns for the fall time (Figure 5). The nonsymmetrical
rise and fall times create approximately 8ns of invalid
data.
The overrange output (D10) is an indication that the
analog input signal has exceeded the positive full-scale
input voltage by 1LSB. When this condition occurs, D10
will switch to logic 1. All other data outputs (D0–D9) will
remain at logic 1 as long as D10 remains at logic 1.
This feature makes it possible to include the MAX1161
in higher-resolution systems.
The MAX1160 EV kit is available to help designers
demonstrate the MAX1160 or MAX1161’s full perfor-
mance. This board includes a reference circuit, clock-
driver circuit, output data latches, and an on-board
reconstruction of the digital data. A separate data sheet
describing the operation of this board is also available.
Contact the factory for price and availability.
Figure 5. Digital Output Characteristics
(ACTUAL)
(EQUIVALENT)
CLK IN
DATA
DATA OUT
OUT
is a registered trademark of Maxim Integrated Products.
2.4V
3.5V
2.4V
0.8V
0.5V
(N - 2)
(N - 2)
N
6ns
typ
14ns typ
t
INVALID
INVALID
DATA
pd1
DATA
(N - 1)
(N - 1)
Overrange Output
Evaluation Board
Digital Outputs
N + 1
INVALID
INVALID
DATA
DATA
t
6ns
RISE
N
N