MAX1124 Maxim Integrated Products, MAX1124 Datasheet - Page 11

• Manufacturer Part Number: MAX1124
• Description: 250Msps Analog-to-Digital Converter
• Manufacturer: Maxim Integrated Products

Figure 4. System and Output Timing Diagram
INP and INN are the fully differential inputs of the
MAX1124. Differential inputs usually feature good rejec-
tion of even-order harmonics, which allows for enhanced
AC performance as the signals are progressing through
the analog stages. The MAX1124 analog inputs are self-
biased at a common-mode voltage of 1.4V and allow a
differential input voltage swing of 1.25V
are self-biased through 2.2kΩ resistors, resulting in a
typical differential input resistance of 4.4kΩ. It is recom-
mended to drive the analog inputs of the MAX1124 in
AC-coupled configuration to achieve best dynamic per-
formance. See the AC-Coupled Analog Inputs section for
a detailed discussion of this configuration.
The MAX1124 features an internal 1.23V bandgap ref-
erence circuit
internal reference-scaling amplifier, determines the full-
scale range of the MAX1124. Bypass REFIO with a
0.1µF capacitor to AGND. To compensate for gain
errors or increase the ADC’s full-scale range, the volt-
age of this bandgap reference can be indirectly adjust-
ed by adding an external resistor (e.g., 100kΩ trim
potentiometer) between REFADJ and AGND or
REFADJ and REFIO. See the Applications Information
section for a detailed description of this process.
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
D0P/N–D9P/N
with LVDS Outputs for Wideband Applications
DCLKN
DCLKP
ORP/N
CLKN
CLKP
INN
INP
t
NOTE: THE ADC SAMPLES ON THE RISING EDGE OF CLKP. THE RISING EDGE OF DCLKP CAN BE USED TO EXTERNALLY LATCH THE OUTPUT DATA.
(Figure
CPDL
- t
______________________________________________________________________________________
PDL
SAMPLING EVENT
~ 0.4 x t
On-Chip Reference Circuit
3), which, in combination with an
Analog Inputs (INP, INN)
SAMPLE
t
N
CPDL
t
AD
N - 8
t
with t
PDL
N - 8
SAMPLE
= 1/f
SAMPLE
P-P
SAMPLING EVENT
t
. Both inputs
LATENCY
N + 1
N - 7
N - 7
Designed for a differential LVDS clock input drive, it is
recommended to drive the clock inputs of the MAX1124
Figure 5. Simplified LVDS Output Architecture
N - 1
SAMPLING EVENT
N + 8
t
CH
t
CPDL
N
- t
PDL
N
2.2kΩ
V
OP
Clock Inputs (CLKP, CLKN)
t
CL
SAMPLING EVENT
2.2kΩ
V
ON
N + 9
N + 1
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N + 1
OGND
OV
CC
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