MAX11040K Maxim Integrated Products, MAX11040K Datasheet - Page 17

• Manufacturer Part Number: MAX11040K
• Description: (MAX11040K / MAX11060) Sigma-Delta ADCs
• Manufacturer: Maxim Integrated Products

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DRDYIN, and DRDYOUT. For single-device applications,
connect CASCIN and DRDYIN to DGND and drive CS
low to transfer data in and out of the devices. With
DRDYIN low, a falling edge at the data-ready signal out-
put (DRDYOUT) indicates that new conversion results
are available for reading in the 96-bit data register. A
falling edge on SCLK clocks in data at DIN. Data at
DOUT changes on the rising edge of SCLK and is valid
on the falling edge of SCLK. DIN and DOUT are trans-
Figure 7. General Read-Operation Timing Diagram
Figure 8. General Write-Operation Timing Diagram
DOUT
SCLK
DIN
CS
DRDYOUT
DRDYIN
DOUT
HIGH-Z
SCLK
DIN
CS
HIGH-Z
t
SU
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
R/W
______________________________________________________________________________________
t
SU
A6 A5
t
DATA READY
DRDY
R/W A6 A5
t
t
PW
DOE
t
PW
t
A4
HD
t
PW
COMMAND ADDRESS
A3 A2 A1 A0
A4
t
SU
t
HD
A3 A2 A1 A0
t
PW
t
SU
t
SCP
Cascadable, Sigma-Delta ADCs
t
DOT
t
CSW
t
DATA LENGTH (NUMBER OF BYTES) DEPENDS ON
CSW
ferred MSB first. Drive CS high to disable the interface
and place DOUT in a high-impedance state.
An interface operation with the devices takes effect on
the last rising edge of SCLK. If CS goes high before the
complete transfer, the write is ignored. Every data
transfer is initiated by the command byte. The com-
mand byte consists of an R/W bit and 7 address bits
(see Table 2.) Figures 7 and 8 show the timing for read
and write operations, respectively.
THE REGISTER BEING WRITTEN (SEE TABLE 2)
DATA LENGTH (NUMBER OF BYTES) DEPENDS
ON THE REGISTER BEING READ (SEE TABLE 2)
t
SCP
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1
B0
HIGH-Z
HIGH-Z
t
CSH1
t
DCD
t
CSH1
17
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