AD9834 Analog Devices, AD9834 Datasheet - Page 5

• Manufacturer Part Number: AD9834
• Description: +2.5V to +5.5V, 50MHz, Low Power (25mW) Complete DDS With on Board Comparator in 20-pin Tssop Package
• Manufacturer: Analog Devices

ANALOG SIGNAL AND REFERENCE
17
19,20 IOUT, IOUTB
POWER SUPPLY
8
9
10
11
Pin # Mnemonic
1
2
3
4
5
6
7
18
DIGITAL INTERFACE AND CONTROL
12
13
14
15
16
REV PrL
FS ADJUST
R E F O U T
COMP
VIN
AVDD
DVDD
CAP/2.5V
D G N D
AGND
MCLK
F S E L E C T
PSELECT
RESET
SLEEP
SDATA
SCLK
FSYNC
SIGN BIT OUT Logic Output. The comparator output is available on this pin or, alternatively, the MSB from
Full-Scale Adjust Control. A resistor (R
the full-scale current is as follows:
Voltage Reference Output.
available at this pin.
A DAC Bias Pin. This pin is used for de-coupling the DAC bias voltage.
Input to comparator. The comparator can be used to generate a square wave from the
sinusoidal DAC output. The DAC output should be filtered appropriately before being applied
to the comparator to improve jitter.
register are set to 1, the comparator input is connected to VIN.
Current Output. This is a high impedance current source. A load resistor of nominally 200
should be connected between IOUT and AGND. IOUTB should preferably be tied through an
external load resistor of 200
to AGND is also recommended to prevent clock feedthrough.
Positive power supply for the analog section. AVDD can have a value from +2.3 V to +5.5 V.
A 0.1 µF decoupling capacitor should be connected between AVDD and AGND.
Positive power supply for the digital section. DVDD can have a value from +2.3 V to +5.5 V.
A 0.1 µF decoupling capacitor should be connected between DVDD and DGND.
The digital circuitry operates from a +2.5 V power supply. This +2.5 V is generated from
DVDD using an on board regulator (when DVDD exceeds +2.7 V).
DVDD is equal to or less than +2.7 V, CAP/2.5 V should be shorted to DVDD.
Digital Ground.
Analog Ground.
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the
frequency of MCLK. The output frequency accuracy and phase noise are determined by this
clock.
Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is
used in the phase accumulator. The frequency register to be used can be selected using the pin
FSELECT or the bit FSEL. When the bit FSEL is being used to select the frequency register,
this pin, FSELECT, should be tied to CMOS high or low.
Phase Select Input. PSELECT controls which phase register, PHASE0 or PHASE1, is added
PSELECT or the bit PSEL. When the phase registers are being controlled by the bit PSEL,
this pin, PSELECT, should be tied to CMOS high or low.
Active high digital input. RESET resets appropriate internal registers to zero which
corresponds to an analog output of midscale. RESET does not affect any of the addressable
registers.
Active high digital input. When this pin is high, the DAC is powered down. This pin has the
same function as control bit SLEEP12.
Serial Data Input. The 16-bit serial data word is applied to this input.
Serial Clock Input. Data is clocked into the AD9834 on each falling SCLK edge.
Active Low Control Input. This is the frame synchronisation signal for the input data. When
FSYNC is taken low, the internal logic is informed that a new word is being loaded into
the device.
the NCO can be output on this pin. Setting bit OPBITEN in the control register to 1 enables
this output pin. Bit SIGNPIB determines whether the comparator output or the MSB from
the NCO is output on the pin.
determines the magnitude of the full-scale DAC current.
decoupling capacitor of typically 100 nF which is connected from CAP/2.5V to DGND.
to the phase accumulator output. The phase register to be used can be selected using the pin
Function
PRELIMINARY TECHNICAL DATA
IOUT
V
REFOUT
FULL-SCALE
PIN FUNCTIONS DESCRIPTIONS
= 1.20 V nominal, R
= 18 x V
The AD9834 has an internal 1.20 V reference, which is made
REFOUT
to AGND but can be tied directly to AGND. A 20pF capacitor
–5–
/R
SET
When bits OPBITEN and SIGNPIB in the control
SET
= 6.8 k
SET
) is connected between this pin and AGND. This
typical
The relationship between R
The regulator requires a
AD9834
SET
and
If