AD9540 Analog Devices, AD9540 Datasheet - Page 7

• Manufacturer Part Number: AD9540
• Description: 655 MHZ Low Jitter Clock Generator
• Manufacturer: Analog Devices

Parameter
DAC OUTPUT CHARACTERISTICS
DAC RESIDUAL PHASE NOISE
I/O Update to SYNC_CLK Setup Time
PS<2:0> to SYNC_CLK Setup Time
Latencies/Pipeline Delays
Resolution
Full-Scale Output Current
Gain Error
Output Offset
Output Capacitance
Voltage Compliance Range
Wideband SFDR (DC to Nyquist)
Narrow-Band SFDR
19.7 MHz F
I/O Update to DAC Frequency Change
I/O Update to DAC Phase Change
PS<2:0> to DAC Frequency Change
PS<2:0> to DAC Phase Change
I/O Update to CP_OUT Scaler Change
I/O Update to Frequency Accumulator
10 MHz Analog Out
40 MHz Analog Out
80 MHz Analog Out
120 MHz Analog Out
160 MHz Analog Out
10 MHz Analog Out (±1 MHz)
10 MHz Analog Out (±250 kHz)
10 MHz Analog Out (±50 kHz)
40 MHz Analog Out (±1 MHz)
40 MHz Analog Out (±250 kHz)
40 MHz Analog Out (±50 kHz)
80 MHz Analog Out (±1 MHz)
80 MHz Analog Out (±250 kHz)
80 MHz Analog Out (±50 kHz)
120 MHz Analog Out (±1 MHz)
120 MHz Analog Out (±250 kHz)
120 MHz Analog Out (±50 kHz)
160 MHz Analog Out (±1 MHz)
160 MHz Analog Out (±250 kHz)
160 MHz Analog Out (±50 kHz)
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
Step Size Change
OUT
Min
7
7
33
33
29
29
4
4
−10
AVDD − 0.50
Rev. 0 | Page 7 of 32
Typ
10
10
5
65
62
57
56
54
83
85
86
82
84
87
80
82
86
80
82
84
80
82
84
122
134
143
150
158
160
Max
15
+10
0.6
AVDD + 0.50
ns
ns
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
Bits
mA
µA
pF
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Unit
SYSCLK Cycles
% FS
Test Conditions/Comments
AD9540