AD9945 Analog Devices, AD9945 Datasheet - Page 8

• Manufacturer Part Number: AD9945
• Description: Complete 12-Bit 40 MHz CCD Signal Processor
• Manufacturer: Analog Devices

AD9945
INTERNAL REGISTER DESCRIPTION
Register
Name
Operation
Control
Clamp Level 0
VGA Gain
NOTE: All register values default to 0x000 at power-up except clamp level, which defaults to 128 decimal (128 LSB clamp level).
Address Bits
A2
0
0
0
A1
0
0
1
1
A0
0
1
0
1
Data Bits
D0
D2, D1
D3
D5, D4
D6
D8, D7
D11 to D9
D0
D1
D2
D3
D4
D5
D6
D11 to D7
D7 to D0
D9 to D0
Function
Software Reset (0 = Normal Operation, 1 = Reset all registers to default)
Power-Down Modes (00 = Normal Power, 01 = Standby, 10 = Total Shutdown)
OB Clamp Disable (0 = Clamp ON, 1 = Clamp OFF)
Test Mode. Should always be set to 00.
PBLK Blanking Level (0 = Blank Output to Zero, 1 = Blank to OB Clamp Level)
Test Mode 1. Should always be set to 00.
Test Mode 2. Should always be set to 000.
SHP/SHD Input Polarity (0 = Active Low, 1 = Active High)
DATACLK Input Polarity (0 = Active Low, 1 = Active High)
CLPOB Input Polarity (0 = Active Low, 1 = Active High)
PBLK Input Polarity (0 = Active Low, 1 = Active High)
Three-State Data Outputs (0 = Outputs Active, 1 = Outputs Three-Stated)
Data Output Latching (0 = Latched by DATACLK, 1 = Latch is Transparent)
Data Output Coding (0 = Binary Output, 1 = Gray Code Output)
Test Mode. Should always be set to 00000.
OB Clamp Level (0 = 0 LSB, 255 = 255 LSB)
VGA Gain (0 = 6 dB, 1023 = 40 dB)
Table I. Internal Register Map
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REV. A