AD9945 Analog Devices, AD9945 Datasheet - Page 11

• Manufacturer Part Number: AD9945
• Description: Complete 12-Bit 40 MHz CCD Signal Processor
• Manufacturer: Analog Devices

CCD MODE TIMING
REV. A
OUTPUT
SIGNAL
CLPOB
DATACLK
DATA
PBLK
OUTPUT
CCD
SIGNAL
DATA
CCD
SHD
SHP
NOTES
1. CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING WITH CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.
NOTES
1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.
2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
EFFECTIVE PIXELS
EFFECTIVE PIXEL DATA
t
ID
t
S1
N–10
t
OD
N
t
ID
Figure 9. Typical CCD Mode Line Clamp Timing
N– 9
OPTICAL BLACK PIXELS
t
S2
N+1
OB PIXEL DATA
Figure 8. CCD Mode Timing
N– 8
t
CP
–11–
N+2
HORIZONTAL
BLANKING
DUMMY PIXELS
DUMMY BLACK
N– 1
N+9
EFFECTIVE PIXELS
EFFECTIVE DATA
AD9945
N
N+10