AD9501 Analog Devices, AD9501 Datasheet - Page 7

• Manufacturer Part Number: AD9501
• Description: Digitally Programmable Delay Generator
• Manufacturer: Analog Devices

REV. A
Ramp charging current and DAC full-scale current are slaved
together in the AD9501 to minimize delay drift over tempera-
ture. To preserve the unit’s low drift performance, both R
and C
which are used should be 1% metal film types.
The programmed delay (t
Graph 1. RC Values vs. Full-Scale Delay Range (t
EXT
should have low temperature coefficients. Resistors
D
) is set by the DAC inputs, D
Figure 3. AD9501 System Timing
0
–D
DFS
SET
)
7
.
–7–
The minimum delay through the AD9501 corresponds to an
input code of 00
programmed delay can be approximated by:
Total delay through the AD9501 for any given DAC code is
equal to:
As shown on the block diagram, TTL/CMOS latches are
included to store the digital delay data. Data is latched when
LATCH is HIGH. When LATCH is LOW, the latches are
transparent, and the DAC will attempt to follow any changes on
inputs D
The System Timing Diagram, Figure 3, shows the timing
relationship between the input data and the latch. The DAC
settling time (t
(Programmed Delay) data is updated, a minimum 30 ns must
elapse between the time LATCH goes high and the arrival of a
TRIGGER pulse to assure rated pulse delay accuracy.
When RESET goes HIGH, the ramp timing capacitor (C
8.5 pF) is discharged. The RESET input is level-sensitive, and
overrides the TRIGGER input. Therefore, any trigger pulse
which occurs when RESET is HIGH will not produce an output
pulse. As shown on the system timing diagram, Figure 3, the
next trigger pulse should not occur before the Linear Ramp
Settling Time (t
delay accuracy.
t
t
TOTAL
D
(DAC code /256) t
0
–D
t
D
7
.
LD
LRS
t
H
PD
) is approximately 30 ns. After the digital
, and FF
) interval is completed to assure rated pulse
H
DFS
gives the full-scale delay. Any
AD9501
EXT
+