USBN9603 National Semiconductor, USBN9603 Datasheet - Page 55

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USBN9603

Manufacturer Part Number
USBN9603
Description
USBN9603 Universal Serial Bus Full Speed Function Controller with Enhanced DMA Support
Manufacturer
National Semiconductor
Datasheet

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8.0 Device Characteristics
8.5 PARALLEL INTERFACE TIMING (MODE1-0 = 01
Note: The setup and hold times t
signals may switch at the same time.
(3.0V< V
Symbol
t
t
t
t
t
t
t
t
t
t
WHAH
WHCH
DHWH
1. Clock Input: CKI = 24 MHz on this device
2. Memory Clock: MCLK = CKI/2 = 12 MHz
DSWL
RHDZ
AHAL
RDLV
CLAL
AVAL
ALRL
t
t
t
CC
WL
AH
RL
< 5.5V, 0˚C < TA< +70˚C, unless otherwise specified)
ALE High Time
Chip Select Low to ALE Low
Address Valid to ALE Low
Address Hold after ALE Low
ALE Low to RD Low
Read Low to Data Valid
Data Hold after Read High
Read Pulse Width
Write High to next ALE High
Write High to CS High
Write Pulse Width
Data Setup to WR High
Data Hold after WR High
D7-0 Input
CS
WR
A0
Parameter
Figure 25. Non-Multiplexed Mode Write Timing
1
AS
(Continued)
and t
t
AS
(Consecutive Write Cycles Shown)
2
AH
are defined relative to the first transition of either CS or WR. All three
t
WW
t
Valid
Conditions
C
C
C
C
C
C
C
C
C
C
C
C
C
DS
L
L
L
L
L
L
L
L
L
L
L
L
L
B
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
)
55
t
t
DH
AH
t
WC
3/MCLK
3/MCLK
1/CKI
1/CKI
1/CKI
1/CKI
Min
10
10
10
25
10
2
Valid
Typ
20
t
WHCH
Max
30
15
Units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
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