USBN9603 National Semiconductor, USBN9603 Datasheet - Page 4

• Manufacturer Part Number: USBN9603
• Description: USBN9603 Universal Serial Bus Full Speed Function Controller with Enhanced DMA Support
• Manufacturer: National Semiconductor

www.national.com
Table of Contents
7.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
7.1.10
7.1.11
7.1.12
7.1.13
7.1.14
TRANSFER REGISTERS .......................................................................................................... 36
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
7.2.11
7.2.12
7.2.13
7.2.14
7.2.15
7.2.16
7.2.17
7.2.18
7.2.19
7.2.20
7.2.21
7.2.22
7.2.23
7.2.24
7.2.25
7.2.26
Revision Identifier (RID) .............................................................................................. 31
Node Functional State Register (NFSR) ..................................................................... 32
Main Event Register (MAEV) ....................................................................................... 32
Main Mask Register (MAMSK) .................................................................................... 33
Alternate Event Register (ALTEV).............................................................................. 33
Alternate Mask Register (ALTMSK) ............................................................................ 34
Transmit Event Register (TXEV) ................................................................................. 34
Transmit Mask Register (TXMSK) ............................................................................... 35
Receive Event Register (RXEV) ................................................................................. 35
Receive Mask Register (RXMSK) ............................................................................... 35
NAK Event Register (NAKEV) .................................................................................... 36
NAK Mask Register (NAKMSK) ................................................................................... 36
FIFO Warning Event Register (FWEV) ....................................................................... 36
FIFO Warning Mask Register (FWMSK) ..................................................................... 37
Frame Number High Byte Register (FNH) .................................................................. 37
Frame Number Low Byte Register (FNL) .................................................................... 37
Function Address Register (FAR) ................................................................................ 38
DMA Control Register (DMACNTRL) .......................................................................... 38
DMA Event Register (DMAEV) .................................................................................... 39
DMA Mask Register (DMAMSK) ................................................................................. 40
Mirror Register (MIR) ................................................................................................... 41
DMA Count Register (DMACNT) ................................................................................. 41
DMA Error Register (DMAERR) .................................................................................. 41
Wake-Up Register (WKUP) ........................................................................................ 42
Endpoint Control 0 Register (EPC0) ............................................................................ 43
Transmit Status 0 Register (TXS0) ............................................................................. 43
Transmit Command 0 Register (TXC0) ..................................................................... 44
Transmit Data 0 Register (TXD0) ................................................................................ 44
Receive Status 0 Register (RXS0) .............................................................................. 44
Receive Command 0 Register (RXC0) ....................................................................... 45
Receive Data 0 Register (RXD0) ................................................................................ 45
Endpoint Control X Register (EPC1 to EPC6) ............................................................. 46
Transmit Status X Register (TXS1, TXS2, TXS3) ....................................................... 46
Transmit Command X Register (TXC1, TXC2, TXC3) ................................................ 47
Transmit Data X Register (TXD1, TXD2, TXD3) ......................................................... 48
Receive Status X Register (RXS1, RXS2, RXS3) ....................................................... 48
Receive Command X Register (RXC1, RXC2, RXC3) ................................................ 49
Receive Data X Register (RXD1, RXD2, RXD3) ......................................................... 50
(Continued)
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