ACS8526LC Semtech Corporation, ACS8526LC Datasheet - Page 37
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ACS8526LC
Manufacturer Part Number
ACS8526LC
Description
Line Card Protection Switch for PDH, Sonet or SDH Systems
Manufacturer
Semtech Corporation
Datasheet
1.ACS8526LC.pdf
(74 pages)
- Current page: 37 of 74
- Download datasheet (604Kb)
Address (hex):
Address (hex):
Revision 4.01/June 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
Register Name
Register Name
Bit No.
Bit No.
Bit 7
[7:6]
[4:3]
[1:0]
Bit 7
[5:0]
5
2
7
6
34
35
cnfg_input_mode
Description
Not used.
XO_edge
If the 12.8 MHz oscillator module connected to
REFCLK has one edge faster than the other, then for
jitter performance reasons, the faster edge should
be selected. This bit allows either the rising edge or
the falling edge to be selected.
Not used.
ip_sonsdhb
Bit to configure input frequencies to be either
SONET or SDH derived. This applies only to
selections of 0001 (bin) in the
cnfg_ref_source_frequency registers when the
input frequency is either 1544 kHz or 2048 kHz.
*The default value of Bit 2 is taken from the value
of the SONSDHB pin at power-up.
Not used.
cnfg_DPLL2_path
DPLL2_dig_
feedback
Description
Not used.
DPLL2_dig_feedback
Bit to select digital feedback mode for DPLL2.
Not used.
Bit 6
Bit 6
XO_edge
Bit 5
Bit 5
Description
Description
Bit 4
Bit 4
FINAL
Page 37
(R/W) Register controlling various
input modes of the device.
(R/W) Register to configure the
feedback mode of DPLL2.
Bit Value
Bit Value
Bit 3
Bit 3
0
1
0
1
0
1
-
-
-
-
-
ip_sonsdhb
Value Description
-
Device uses the rising edge of the external
oscillator.
Device uses the falling edge of the external
oscillator.
-
SDH- inputs set to 0001 expected to be 2048 kHz.
SONET- inputs set to 0001 expected to be
1544 kHz.
-
Value Description
-
DPLL2 in analog feedback mode.
DPLL2 in digital feedback mode.
-
Bit 2
Bit 2
ACS8526 LC/P LITE
Default Value
Default Value
Bit 1
Bit 1
DATASHEET
www.semtech.com
1100 0010*
0100 0000
Bit 0
Bit 0
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