ACS406CS Semtech Corporation, ACS406CS Datasheet - Page 21

• Manufacturer Part Number: ACS406CS
• Description: Two-chip Fiber Optic Modem Ics / ACS4060 100-pin Tqfp, ACS9010 44-pin TQFP
• Manufacturer: Semtech Corporation

Pin Description ACS4060 part 3
Pin
57
56
55
85
86
90
89
87
88
44
45
52
54
91
81
51
ERRC
ERRL
LOSS
Frame
CKM
SETB
Fhold
CM2
CM3
CKC
CM1
DR1
DR3
Sym
DR2
DR4
DR5
IO
O
O
O
I
I
I
I
I
I
I
Configuration
Select
Clock Select
Clock Select
Signal
Modes
Error Latch
Error count
Data Rate
LASER set-up
LOSS of
Frame Mode
Format Hold
Name
CM1,CM2,CM3 select the
Configuration Modes such as
8B10B coding rules ERRL will
out of synchronisation e.g.
8B10B coding rules. Errors may
external electronic counter.
The DR(5:1) input select the
Data Rates and number of
channels. See section headed
Data Rate Selection.
When CKC = 0, TCLK1/2/3/4
is configured as an output.
When CKC = 1, TCLK1/2/3/4
is configured as an input.
When CKM = 0,
TmCLK1/2/3/4 is configured as
an output.
When CKM = 1,
TmCLK1/2/3/4 is configured as
an input
SETB = 0, to adjust the
LASER output power.
SETB = 1, in operational mode.
When LOSS = 1, receive data
is unreliable.
When LOSS = 0, receive data
is reliable.
When Frame = '1' , Support
channels are configured in frame
mode.
When Fhold = '0', the device is
configured for asymmetrical data
communication.The most
common setting for this input is
Fhold = '1' supporting
symmetrical communications.
full duplex, master and slave
mode.
If errors are detected in the
be forced high.. ERRL will be
reset low if the device is forced
PORB = 0.
ERRC will go high coincident
with each error detected in the
be accumulated by means of an
Description
21
Pin Description ACS4060 part 4
Pin
75
74
71
37
63
66
38
43
48
53
83
78
73
68
DM1C1
DM2C1
DM1C2
DM2C2
DM1C3
DM2C3
DM1C4
DM2C4
SCEXT
Rxdat-
ECLK
POL2
POL1
IREF
Sym
IO
I
I
I
I
I
I
I
I
I
Select Clock
Current
CLK1
CLK1
CLK2
CLK2
CLK3
CLK3
CLK4
CLK4
Polarity
External
External Clock
reference
Rxdat -ve
input
Diag. mode 1
Diag. mode 2
Diag. mode 1
Diag. mode 2
Diag. mode 1
Diag. mode 2
Diag. mode 1
Diag. mode 2
Name
Defines the polarity of input
signal TPOS/TNEG.
NRZ,HDB3, B8SZ or AMI.
When SCEXT = '1' , then the
system clock will be the external
clock applied to input 'ECLK'.
When SCEXT = '0' , then the
system clock will be the crystal
clock generated at XTI/XTO.
External system clock input.
Only valid when SCEXT = '1'.
Clock must have at least 40%
High and 40% Low time.
A 51K
placed between IREF and
GND.
This determines the slicing level
for input Rxdat+. Should be set
at DVDD/2. On the next
generation of devices this is
likely to be derived from the
ACS9010 device . Backward
compatibilty will be maintained.
Diagnostic mode selection pin
for data channels associated
with TxCLK1.
Diagnostic mode selection pin
for data channels associated
with TxCLK2.
Diagnostic mode selection pin
for data channels associated
with TxCLK3.
Diagnostic mode selection pin
for data channels associated
with TxCLK4.
ACS406CS Issue 1.6 January 1999.
Description
1% resistor should be