ACS406CS Semtech Corporation, ACS406CS Datasheet - Page 15

• Manufacturer Part Number: ACS406CS
• Description: Two-chip Fiber Optic Modem Ics / ACS4060 100-pin Tqfp, ACS9010 44-pin TQFP
• Manufacturer: Semtech Corporation

Jitter Characteristics
The transmit path contains a Transmit FIFO, which
acts to attenuate high frequency input jitter components
of the order 1kHz or greater.
The receive path contains a Digital Phase Locked
Loop (D_PLL), which controls the output frequency of
the receive clock in order to track the transmit clock
frequency at the far end modem. The D_PLL also acts
to:-
1) maintain the fill level in the receive FIFO, to ensure
that the data latency stays within the specified limits.
2) ensure that Jitter Tolerance and Jitter Attenuation is
within ITU G.823 and AT&T 62411 specifications.
3) accommodate any clock drift that may be present.
The performance boundary of the D_PLL is ±500 ppm.
The ±500 ppm performance limit includes jitter
attenuation and drift accommodation.
The oscillator controlled by the Digital Phase Locked
Loop operates in steps of 8ppm, and therefore has a
resolution down to +/- 4ppm. Due to the discrete
nature of the frequency changes, the period of the
receive clock can change by +/- one system clock
cycle. In the absence of input jitter, output jitter
generation for E1 remote loopback configuration is
measured at 0.40UIpp over frequency range 20Hz to
100kHz, and 0.08UIpp over frequency range 18kHz to
100kHz.
The E1 Jitter Transfer plot is shown below, measured
worst case, Remote Loopback.
-10
-20
-30
-40
-50
-60
-70
1.00E+00
10
0
1.00E+01
1.00E+02
E1 Jitter Transfer Plot
Frequency (Hz)
15
1.00E+03
1.00E+04
ACS406CS Issue 1.6 January 1999.
1.00E+05