S2062 AMCC (Applied Micro Circuits Corp), S2062 Datasheet - Page 8

• Manufacturer Part Number: S2062
• Description: Dual Serial Backplane Device
• Manufacturer: AMCC (Applied Micro Circuits Corp)

Reference Clock Input
The reference clock input must be supplied with a
low-jitter clock source. All reference clocks in a sys-
tem must be within 200 ppm of each other to insure
that the clock recovery units can lock to the serial
data.
The frequency of the reference clock must be either
1/10 the serial data rate, CLKSEL = 0, or 1/20 the
serial data rate, CLKSEL=1. In both cases the fre-
quency of the parallel word rate output, TCLKO, is
constant at 1/10 the serial data rate. See Table 5.
Serial Data Outputs
The S2062 provides LVPECL level serial outputs. Each
high speed output should be provided with a resistor to
VSS (Gnd) near the device. A value of 4.5 K provides
optimal performance with minimum impact on power
dissipation. The resistance may be as low as 450
but this will dissipate additional power with no sub-
stantive performance improvement. Outputs are de-
signed to perform optimally when AC-coupled.
8
S2062
Table 3. K Character Generation (SOFx = 0)
C
h
K
K
K
K
K
K
K
K
K
K
K
K
a
2
2
2
2
2
2
2
2
2
2
2
3
a r
K
8
8
8
8
8
8
8
8
3
7
9
0
Table 4. Data to 8B/10B Alphabetic Representation
t c
0 .
1 .
2 .
3 .
4 .
5 .
6 .
7 .
7 .
7 .
7 .
7 .
r e
8
B
1 /
0
0
0
0
1
1
1
1
1
1
1
1
0
D
0
0
1
1
0
0
1
1
1
1
1
1
B
0
1
0
1
0
1
0
1
1
1
1
1
N I
I D
A
1
1
1
1
1
1
1
1
1
1
1
1
p l
[ N
[
: 7
1
1
1
1
1
1
1
1
0
1
1
1
h
1
1
1
1
1
1
1
1
1
0
1
1
: 0
a
] 0
0
0
0
0
0
0
0
0
1
1
0
1
n
] 9
0
0
0
0
0
0
0
0
1
1
1
0
u
m
r o
r e
D
c i
K
O
G
R
U
1
1
1
1
1
1
1
1
1
1
1
1
E
e
[ T
p
N
: 0
e r
] 9
s
e
t n
C
1
1
1
1
1
1
1
1
0
0
0
1
t a
a
1
1
1
1
1
1
1
1
0
0
1
0
r u
o i
,
b
0
0
0
0
0
0
0
0
0
1
0
0
n
c
0
0
0
0
0
0
0
0
1
0
0
0
e r
d
0
0
0
0
0
0
0
0
0
0
0
0
t n
i e
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
0
1
0
0
0
0
0
g f
R
Transmit FIFO Initialization
The transmit FIFO must be initialized after stable
delivery of data and TCLK to the parallel interface,
and before entering the normal operational state of
the circuit. FIFO initialization is performed upon the
de-assertion of the RESET signal. TCLKO will oper-
ate normally regardless of the state of RESET.
Table 5. Operating Rates
Note: SDR = Serial Data Rate.
0
1
0
1
1
1
0
1
1
1
1
1
D
j h
1
1
1
0
0
0
0
1
1
1
1
1
0
a
R
+
1
0
0
0
1
1
1
1
1
1
1
1
A
0
0
1
1
T
E
DUAL SERIAL BACKPLANE DEVICE
1
b
2
c
C
0
0
0
0
0
0
0
0
1
1
1
0
C
a
L
0
0
0
0
0
0
0
0
1
1
0
1
K
r u
b
0
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
3
d
S
c
E
1
1
1
1
1
1
1
1
0
1
1
1
e r
d
D
L
1
1
1
1
1
1
1
1
1
1
1
1
i e
a
t n
1
1
1
1
1
1
1
1
0
0
0
0
4
e
a t
0
1
0
0
0
1
0
1
1
1
1
1
g f
R
1
0
1
0
0
0
1
0
0
0
0
0
B
F
R
e r
D
j h
5
S
S
S
S
0
0
0
1
1
1
1
0
0
0
0
0
y
i
E
D
D
D
D
q
0
1
1
1
0
0
0
0
0
0
0
0
e t
-
F
u
R
R
R
R
C
e
1 /
2 /
1 /
2 /
L
n
6
f
0
0
0
0
K
c
y
S
7
g
June 20, 2000 / Revision B
y
C
n
0
0
S
0
0
3 .
3 .
o
7 .
7 .
c
e
i r
9
9
8
h
m
7
7
0 -
0 -
C
l a
–
–
R
1
1
m
a
6 .
6 .
h
O
3 .
3 .
e t
5
5
u
a
9
e
j
G
G
p t
G
G
a r
n
H
H
H
H
t u
z
z
s t
z
z
t c
r e
F
e r
T
S
S
S
S
C
D
D
D
D
q
L
u
R
R
R
R
K
e
1 /
1 /
1 /
1 /
n
O
0
0
0
0
c
y