S2062 AMCC (Applied Micro Circuits Corp), S2062 Datasheet

S2062

Manufacturer Part Number

S2062

Description

Dual Serial Backplane Device

Manufacturer

AMCC (Applied Micro Circuits Corp)

Datasheet

1.S2062.pdf (27 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

S2062TB

Manufacturer:

AMCC

Quantity:

1 831

Current page: 1 of 27
Download datasheet (336Kb)

June 20, 2000 / Revision B

FEATURES

APPLICATIONS

Figure 1. Typical Dual Gigabit Ethernet Application

DEVICE

SPECIFICATION

DUAL SERIAL BACKPLANE DEVICE

• Broad operating rate range (0.77 - 1.3 GHz)

• Dual Transmitter with phase-locked loop (PLL)

• Dual Receiver PLL provides clock and data

• Internally series terminated TTL outputs

• On-chip 8B/10B line encoding and decoding for

• 2x8 Bit parallel TTL interface

• Low-jitter serial PECL interface

• Local Loopback

• Interfaces with coax, twinax, or fiber optics

• Single +3.3V supply, 1.37 W power dissipation

• Compact 21mm x 21mm 156 TBGA package

• Ethernet Backbones

• Workstation

• Frame buffer

• Switched networks

• Data broadcast environments

• Proprietary extended backplanes

INTERFACE

ETHERNET

- 1062 MHz (Fibre Channel)

- 1250 MHz (Gigabit Ethernet) line rates

- 1/2 Rate Operation

clock synthesis from low speed reference

recovery

two separate parallel 8-bit channels

GIGABIT

DUAL

GE INTERFACE

S2068

GENERAL DESCRIPTION

The S2062 facilitates high-speed serial transmission

of data in a variety of applications including Gigabit

Ethernet, Fibre Channel, serial backplanes, and pro-

prietary point to point links. The chip provides two

separate transceivers which can be operated indi-

vidually for a data capacity of >2 Gbps.

Each bi-directional channel provides 8B/10B coding/

decoding, parallel to serial and serial to parallel con-

version, clock generation/recovery, and framing. The

on-chip transmit PLL synthesizes the high-speed

clock from a low-speed reference. The on-chip dual

receive PLL is used for clock recovery and data re-

timing on the two independent data inputs. The

transmitter and receiver each support differential

PECL-compatible I/O for copper or fiber optic com-

ponent interfaces with excellent signal integrity. Lo-

cal loopback mode allows for system diagnostics.

The chip requires a 3.3V power supply and dissi-

pates 1.37 watts.

Figure 1 shows the S2062 and S2068 in a Gigabit

Ethernet application. Figure 2 combines the

S2062 with a crosspoint switch to demonstrate a

serial backplane application. Figure 3 is the input/

output diagram. Figures 4 and 5 show the transmit

and receive block diagrams, respectively.

MAC

(ASIC)

MAC

(ASIC)

SERIAL BP DRIVER

S2062

TO SERIAL BACKPLANE

S2062

Related parts for S2062

Related keywords

S2062 datasheet
S2062 data sheet
S2062 pdf datasheet
S2062 component
S2062 part
S2062 distributor
S2062 RoHS
S2062 datasheet download