SM4M64DT-10 Enhanced Memory Systems, Inc., SM4M64DT-10 Datasheet - Page 2

• Manufacturer Part Number: SM4M64DT-10
• Description: 168-pin Enhanced SDRAM DIMM 32MB DIMM
• Manufacturer: Enhanced Memory Systems, Inc.

168-pin Enhanced SDRAM DIMM
8MB, 16MB, 32MB DIMM
Pin Descriptions
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: [phone];
Page 2 of 13
Symbol
CK0,1,2,3
CKE0,1
S0,1,2,3#
RAS#, CAS#,
WE#
BA0
A0-A10
DQ0-DQ63
DQMB0-7
V
V
SDA
SCL
SA0-2
WP
RFU
DU
NC
DD
SS
Output
Supply
Supply
Output
Type
Input/
Input/
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
-
-
-
Clocks: All ESDRAM input signals are sampled on the positive edge of CK.
Clock Enables: CKE activates (high) or deactivates (low) the CK signals. Deactivating the clock initiates the
Power-Down and Self-Refresh operations (all banks idle), or Clock Suspend operation. CKE is synchronous until
the device enters Power-Down and Self-Refresh modes where it is asynchronous until the mode is exited.
Chip Select: S# enables (low) or disables (high) the command decoder. When the command decoder is
disabled, new commands are ignored but previous operations continue.
Command Inputs: Sampled on the rising edge of CK, these inputs define the command to execute.
Bank Address: This input defines to which bank a command is applied.
Address Inputs: A0-A10 define the row address during the Bank Activate command. A0-A8 define the column
address during Read and Write commands. A10/AP invokes the Auto-Precharge operation. During manual
Precharge commands, A10/AP low specifies a single bank precharge while A10/AP high precharges all banks.
The address inputs are also used to program the Mode Register.
Data I/O: Data bus inputs and outputs. For Write cycles, input data is applied to these pins and must be set-up
and held relative to the rising edge of clock. For Read cycles, the device drives output data on these pins after
the CAS latency is satisfied.
Data I/O Mask Inputs: DQMB0-7 inputs mask write data (zero latency) and acts as a synchronous output enable
(2-cycle latency) for read data.
Power Supply: +3.3 V
Ground
Serial Presence-Detect Data: SDA is a bi-directional pin used to transfer addresses and data into
and data out of the presence-detect portion of the module.
Serial Clock for Presence-Detect: SCL is used to synchronize the presence detect data transfer to
and from the module
Presence-Detect Address Inputs: These pins are used to configure the presence detect device.
Serial Presence Detect Write Protect: Active high inhibits writes to the SPD EEPROM. WP must be driven low
for normal read/write operations.
Reserved for Future Use: These pins should be left unconnected.
Do not use.
No connect - open pin.
http://www.edram.com
Function
The information contained herein is subject to change without notice.
1999 Enhanced Memory Systems. All rights reserved.
Preliminary Data Sheet
Revision 3.1