IDT82P2284 Integrated Device Technology, Inc., IDT82P2284 Datasheet - Page 78

• Manufacturer Part Number: IDT82P2284
• Description: 4 Channel T1/J1/E1 Transceiver
• Manufacturer: Integrated Device Technology, Inc.

IDT82P2284
3.18.2
plexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the
TSDn pin is used to input the data to each link at the bit rate of 2.048
Mb/s. While in the Multiplexed Mode, the data is byte interleaved from
one high speed data stream and inputs on the MTSDA1 (MTSDB1) pins
at the bit rate of 8.192 Mb/s.
the transmit line side are timed to a same clock source, the Transmit
System Interface is in Transmit Clock Master mode. If the transmit sys-
tem interface and the transmit line side are timed to different clock
Table 43: Operating Modes Selection In E1 Transmit Path
3.18.2.1
signal on the TSCKn pin and framing pulse on the TSFSn pin to input
the data on each TSDn pin. The signaling bits on the TSIGn pin are per-
timeslot aligned with the data on the TSDn pin.
face is clocked by the TSCKn. The active edge of the TSCKn used to
update the pulse on the TSFSn is determined by the FE bit. The active
edge of the TSCKn used to sample the data on the TSDn and TSIGn is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the TSFSn is ahead.
Basic frame, CRC Multi-frame and/or Signaling Multi-frame. The indica-
tions are selected by the FSTYP bit. The active polarity of the TSFSn is
selected by the FSINV bit.
mit Clock Master Full E1 mode and Transmit Clock Master Fractional E1
mode.
3.18.2.1.1
Master mode, the special feature in this mode is that the TSCKn is a
standard 2.048 MHz clock, and the data in all 32 timeslots in a standard
E1 frame are clocked in by the TSCKn.
NOTE:
1. When the G56K, GAP bits in TPLC indirect registers are set, the PCCE bit must be set to ‘1’.
2. In Transmit Multiplexed mode, two sets of multiplexed data and signaling pins (A and B) are provided for one multiplexed bus. Their functions are the same. One is the backup for the
other. One set is selected by the MTSDA bit when used.
TMUX
0
1
In E1 mode, the Transmit System Interface can be set in Non-multi-
In the Non-multiplexed mode, if the transmit system interface and
In the Transmit Clock Master mode, each link uses its own timing
In the Transmit Clock Master mode, the data on the system inter-
In the Transmit Clock Master mode, the TSFSn can indicate the
The Transmit Clock Master mode includes two sub-modes: Trans-
Besides all the common functions described in the Transmit Clock
E1 MODE
TMODE
Transmit Clock Master Mode
X
0
1
Transmit Clock Master Full E1 Mode
not both 0s
G56K, GAP
00
X
X
1
Transmit Clock Master Full E1
Transmit Clock Master Fractional E1
Transmit Clock Slave
Transmit Multiplexed
Operating Mode
67
sources, the Transmit System Interface is in Transmit Clock Slave
mode.
the entire E1 frame, the Transmit System Interface is in Transmit Clock
Master Full E1 mode. If only the clocks aligned to the selected timeslots
are output on TSCKn, the Transmit System Interface is in Transmit
Clock Master Fractional E1 mode.
each link into various operating modes and the pins’ direction of the
transmit system interface in different operating modes.
3.18.2.1.2
Master mode, the special feature in this mode is that the TSCKn is a
gapped 2.048 MHz clock (no clock signal during the selected timeslot).
selecting the G56K & GAP bits in the Transmit Payload Control. The
data in the corresponding gapped duration is a don't care condition.
3.18.2.2
pin and the framing pulse on the TSFSn pin to input the data on the
TSDn pin are provided by the system side. When the TSLVCK bit is set
to ‘0’, each link uses its own TSCKn and TSFSn; when the TSLVCK bit
is set to ‘1’ and all four links are in the Transmit Clock Slave mode, the
four links use the TSCK[1] and TSFS[1] to input the data. The signaling
bits on the TSIGn pin are per-timeslot aligned with the data on the TSDn
pin.
is clocked by the TSCKn. The active edge of the TSCKn used to sample
the pulse on the TSFSn is determined by the FE bit. The active edge of
the TSCKn used to sample the data on the TSDn and TSIGn is deter-
mined by the DE bit. If the FE bit and the DE bit are not equal, the pulse
on the TSFSn is ahead. The speed of the TSCKn can be selected by the
CMS bit to be the same rate as the data rate on the system side (2.048
Mb/s) or double the data rate (4.096 Mb/s). If all four links use the
TSCK[1] and TSFS[1] to input the data, the CMS bit of the four links
should be set to the same value. If the speed of the TSCKn is double the
data rate, there will be two active edges in one bit duration. In this case,
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
In the Transmit Clock Master mode, if TSCKn outputs pulses during
Table 43 summarizes how to set the transmit system interface of
Besides all the common functions described in the Transmit Clock
The TSCKn is gapped during the timeslots or the Bit 8 duration by
In the Transmit Clock Slave mode, the timing signal on the TSCKn
In the Transmit Clock Slave mode, the data on the system interface
MTSIGA[1] (MTSDB[1], MTSIGB[1])
Transmit Clock Slave Mode
TSCKn, TSFSn, TSDn, TSIGn
MTSCK, MTSFS, MTSDA[1],
Transmit Clock Master Fractional E1 Mode
TSDn, TSIGn
Input
Transmit System Interface Pin
2
TSCKn, TSFSn
March 22, 2004
Output
X
X