S8501 AMCC (Applied Micro Circuits Corp), S8501 Datasheet - Page 2
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S8501
Manufacturer Part Number
S8501
Description
Hd-sdi Data Retimer
Manufacturer
AMCC (Applied Micro Circuits Corp)
Datasheet
1.S8501.pdf
(18 pages)
S8401/S8501 OVERVIEW
The S8401 transmitter and S8501 receiver provide
serialization and deserialization functions for
scrambled data to implement a HD-SDI. Operation of
the S8401/S8501 chips is straightforward, as depicted
in Figure 2. The sequence of operations is as follows:
Transmitter
Receiver
The 20-bit parallel data handled by the S8401 and
S8501 devices should be from a DC-balanced en-
coding scheme, such as the scrambling as defined
by SMPTE-292M.
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figure 5.
A lock detect feature is provided on the receiver, which
indicates that the PLL is locked (synchronized) to the
data stream.
Figure 3. S8401 Functional Block Diagram
2
S8401/S8501
1. 20-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
1. Clock and data recovery from serial input
2. Serial-to-parallel conversion
3. 20-bit parallel output
REFCLK
D[19:0]
TEST
OE0
OE1
20
D
CONTROL
Q
LOGIC
HIGH DEFINITION SERIAL DIGITAL INTERFACE (HD-SDI) CHIPSET
10
10
MULTIPLIER
F 0 = F 1 X 20
PLL CLOCK
2:1
10
REGISTER
SHIFT
DIVIDE-BY-20
Loopback
Local loopback is supported by the chipset, and pro-
vides a capability for performing offline testing of the
interface to ensure the integrity of the serial channel
before enabling the transmission medium. It also al-
lows for system diagnostics.
Figure 2. Interface Diagram
S8401 TRANSMITTER
Architecture/Functional Description
The S8401 transmitter accepts parallel input data and
serializes it for transmission over fiber optic or coaxial
cable media. The S8401 is compliant with SMPTE
292M Specification, and supports the HD-SDI data
rate of 1.485 Gb/s.
The parallel input data word is 20 bits wide. A block
diagram showing the basic chip function is shown in
Figure 3.
REFCLK
Parallel
Data In
20 Bit
TCLK
Transmitter
S8401
Loopback
December 10, 1999 / Revision C
Serial
Data
Loopback
Receiver
S8501
Detect
Lock
TX
TY
TLX
TLY
TCLK
TCLKN
Parallel
Data Out
RCLK
RCLKN
REFCLK