S8501 AMCC (Applied Micro Circuits Corp), S8501 Datasheet
S8501
Related parts for S8501
S8501 Summary of contents
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... Scrambler Serializer December 10, 1999 / Revision C GENERAL DESCRIPTION The S8401 and S8501 transmitter and receiver pair are designed to perform HD-SDI over fiber optic or coaxial cable interfaces conforming to the require- ments of the SMPTE 292M. The chipset supports 1.485 Gb/s with an associated 20-bit data word. ...
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... Clock and data recovery from serial input 2. Serial-to-parallel conversion 3. 20-bit parallel output The 20-bit parallel data handled by the S8401 and S8501 devices should be from a DC-balanced en- coding scheme, such as the scrambling as defined by SMPTE-292M. Internal clocking and control functions are transpar- ent to the user. Details of data timing can be seen in Figure 5 ...
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... The shift register is clocked by the internally gener- ated bit clock which is 20 times the REFCLK input frequency. The state of the serial outputs is controlled by the output enable pins, OE0 and OE1. D[0] is transmitted first. Figure 4. S8501 Functional Block Diagram LOCKREFN REFCLK RX RY 2:1 ...
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... Received data from the incoming bit stream is provided on the device’s parallel data outputs. The S8501 accepts serial encoded data from a fiber optic or coaxial cable interface. The serial input stream is the result of the serialization of scrambled data by a compatible transmitter ...
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... It also allows system diagnostics. Operating Frequency Range The S8401 and S8501 are optimized for operation at the HD-SDI rate of 1.485 Gb/s. A REFCLK must be selected to be within 100 ppm of the desired byte or word clock rate. ...
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... S8401/S8501 HIGH DEFINITION SERIAL DIGITAL INTERFACE (HD-SDI) CHIPSET Table 4. S8401 Pin Assignment and Descriptions ...
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... S8401/S8501 7 ...
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... S8401/S8501 HIGH DEFINITION SERIAL DIGITAL INTERFACE (HD-SDI) CHIPSET Table 5. S8501 Pin Assignment and Descriptions ...
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... HIGH DEFINITION SERIAL DIGITAL INTERFACE (HD-SDI) CHIPSET Table 5. S8501 Pin Assignment and Descriptions (Continued – – ...
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... S8401/S8501 HIGH DEFINITION SERIAL DIGITAL INTERFACE (HD-SDI) CHIPSET Figure 7. S8401 and S8501 52 PQFP Pinouts OE1 1 OE0 2 ECLIOVCC 3 TLY 4 TLX 5 ECLIOVEE 6 S8401 ECLIOVEE TOP VIEW TY 9 ECLIOVCC 10 TCLKN 11 TCLK 12 ECLVEE 13 TTLVCC = +3.3V AVCC = +3.3V ECLVCC = +3.3V ECLIOVCC = +3.3V ECLIOVEE = 0V TTLGND = 0V ECLVEE = 0V AVEE = ECLVCC ECLVEE ...
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... HIGH DEFINITION SERIAL DIGITAL INTERFACE (HD-SDI) CHIPSET Figure 8. 52 PQFP — (10mm x 10mm) Plastic Quad Flat Pack Thermal Management Note: S8501 package has internal heat spreader resulting in lower ja. December 10, 1999 / Revision ...
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... S8401/S8501 HIGH DEFINITION SERIAL DIGITAL INTERFACE (HD-SDI) CHIPSET Table 6. Absolute Maximum Ratings ...
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... Supply Current P D Power Dissipation V INCLK Single-ended REFCLK input swing Serial Output Voltage Swing V OUT Table 9. S8501 DC Characteristics Parameters Description Output High Voltage (TTL – 3.3V Power Supply – 3.3V Power Supply Output Low Voltage (TTL – 3.3V Power Supply ...
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... S8401/S8501 HIGH DEFINITION SERIAL DIGITAL INTERFACE (HD-SDI) CHIPSET Timing The data on the TX[19:0] data bus will be sampled on every rising edge of REFCLK. The data will be serialized and transmitted onto the serial link. The figure below illustrates the timing requirements of REFCLK with respect to the TX[19:0] signals, minimum high and low durations, and the rising and falling slew rate magnitudes ...
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... When the S8501 is in frequency lock (either with REFCLK or a serial data stream) and LOCKREFN has been inactive for at least 2500 baud times the minimum instantaneous period shall always be greater that 13 ...
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... S8401/S8501 HIGH DEFINITION SERIAL DIGITAL INTERFACE (HD-SDI) CHIPSET Table 13. S8501 Receiver Timing Table ...
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... December 10, 1999 / Revision C Figure 14. TTL Input Rise and Fall Time 90% 80% 50% 50% 20% 10 Figure 15. S8501 Receiver Input Eye Diagram Jitter Mask 0.1 f Backplane Amplitude 0.1 f Figure 16. S8501 – If RY/X or RLY/X not used S8401/S8501 90% 50% 10 Bit Time Vcc RLX 10K ...
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... S8401/S8501 HIGH DEFINITION SERIAL DIGITAL INTERFACE (HD-SDI) CHIPSET Ordering Information GRADE TRANSMITTER S – commercial 8401 GRADE RECEIVER S – commercial 8501 X Grade Part number Example: S8401QF—S8401 PQFP package shipped in trays. Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 • ...