S3045 AMCC (Applied Micro Circuits Corp), S3045 Datasheet - Page 6

• Manufacturer Part Number: S3045
• Description: S3045 Sonet/sdh Oc-48 to Oc-12 Mux/demux Evaluation Board
• Manufacturer: AMCC (Applied Micro Circuits Corp)

S3045
SONET/SDH OC-48 TO OC-12 MUX/DEMUX EVALUATION BOARD
Kill Receive Clock Input [42_KILLRXCLK] – For normal board operation set KILLRXCLK “high.” When this
input is low it will force RX311MCK and POCLK outputs to a logic “0” state.
Line Loopback Enable [42_LLEB] – Active low. For normal board operation set low. Selects Line Loopback.
When active the S3042 will enable the data on the LLD/LLCLK outputs.
Parity Frame Pulse Select [45_PARFPTXSEL] – Default setting for the board is low. When low parity is
calculated over the data bus PIN <7:0> A,B,C,D. When high parity is calculated over the PIN <7:0> A,B,C,D data
bus and the Transmit Input Frame Pulse (TIFP A,B,C,D).
Parity Frame Pulse Receive Select [45_PARFPRXSEL] – Default setting for the board is low. When low parity
is calculated over the data POUT <7:0> A,B,C,D. When high parity is calculated over the data POUT <7:0>
A,B,C,D and the frame pulse (FP A,B,C,D) output.
LED’S
The static status pins such as LOF (D6), OOF (D11), B1ERR (D4), LOS (D5) are available as LED indictors and
as test points. The LED versions of the alarms are held in the active state longer than the actual alarms last so
that the LED’S are able to turn on.
Parallel Output Header Terminals
The parallel outputs POUTA,B,C,D[7:0] (J23, J24, J25, J26) from the S3045 are available at the 2 x 5 pin header
arrays.
Signal Detect - The SD line should be tied to a static value. Table 2 shows how the signal detect can be
configured.
J29 – This connector is used at the factory for FPGA programming.
JP2 and JP1 – These jumpers are for the External or internal clock for the S3040’s as described in Table 2.
JP6 – When strapped for logic “0” the S3040 (U4) serial clock output is forced to lock to REFCLK. Strapped for
logic “1”, the S3040 (U4) locks to the incoming data stream SERDATIP/N.
JP7 – When strapped for a logic “0” the S3040 (U5) serial clock output is forced to lock to REFCLK. Strapped for
a logic “1”, the S3040 (U5) locks to the incoming data stream SERDATIP/N.
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