S3045 AMCC (Applied Micro Circuits Corp), S3045 Datasheet - Page 5

• Manufacturer Part Number: S3045
• Description: S3045 Sonet/sdh Oc-48 to Oc-12 Mux/demux Evaluation Board
• Manufacturer: AMCC (Applied Micro Circuits Corp)

SONET/SDH OC-48 TO OC-12 MUX/DEMUX EVALUATION BOARD
S3045
Dip Switch Settings
The S3045 Evaluation Board is equipped with two DIP switch modules (S2 and S3), to control the static control
functions of the on-board devices. For these DIP switches the OFF (open = “1”) condition asserts a logic low on
the assigned signal, and the ON (closed = “0”) condition asserts a logic high.
S1:
RESET Toggle Switch – This momentary contact switch controls the master reset for the S3041/42/45.
S2:
Parity Select [45_PARSEL] – When high selects even parity. When low selects odd parity.
Scramble Enable [45_SCRBENB] – When low the frame synchronous scrambler is enabled. When high the
scrambler is disabled.
Descrambler Enable [45_DSCRBENB] – When low the frame synchronous descrambler is enabled. When high
the frame synchronous descrambler is disabled.
B2/M1 Parity Byte and Parity count select [45_B2/M1SEL] – When high the B2/M1 byte calculations and
insertions are disabled. When low B2 and M1 calculations and insertions are enabled.
Squelch Clock Mode [45_SQUELCH] – Active low. Set inactive when a clock recovery device used provides a
continuous clock during signal loss or reacquisition. Set active when the clock recovery device used does not
provide a continuous clock during signal loss or signal acquisition. When active and SDLVPECL/SDLVTTL is
inactive, the transmitter serial clock (311TCLK) will be used to maintain timing in the receiving section. When
active and SDLVPECL/SDLVTTL is also active, the 311CLKIN is used for all receiver timing. When active there
is a 3.2 ns shortening or lengthening of the POCLK cycle.
B1 Parity Byte Select [45_B1SEL] – When low B1 calculation and insertion is enabled. When high B1
calculation and insertion is disabled.
Frame Pulse Select [45_FPSEL] – For normal board operation set low. When low the FRAME input is used to
generate the FP A,B,C,D pulse when the third A2 byte is output. When high the FP A,B,C,D output is internally
generated using the A1A2 frame boundary. The FP A,B,C,D is asserted high when the third A2 (28h) byte is
output.
Section-Trace Insertion Select [45_J0/Z0SEL] – Select pins, select section-trace bytes J0/Z0 options. When
low the J0/Z0 bytes are passed through with no modification. When high byte 1 of 48 (J0 bytes) is passed
through with no modification (transparent) and bytes 2 through 48 (Z0 bytes) are filled with the values of 02hex
to 30hex (48 decimal) respectively.
S3:
Test Clock Enable [41_TESTEN] – For normal board operation set high. When high this input will select the
LLCLK input instead of the internally generated 2.4 GHz clock as the system clock. When this input is Low it will
select the internally generated 2.4 GHz clock from the LLCLK input.
Kill Transmit Clock Input [41_KILLTXCLKN] – For normal board operation set high. When low this input will
force the PCLKP/N and PULSE0P/N outputs low.
Line Loopback Enable [41_LLEB] – For normal board operation set high. Selects Line Loopback when low.
When LLEB is low the S3041 will force the data from the LLD/LLCLK inputs from the S3042 to the TSD/TSCLK
outputs of the S3042.
Frame Enable Input [42_FRAMEN] – For normal board operation set FRAMEN high. This enables the frame
detector circuit to detect A1 A2 alignment and lock to word boundary. When this input is low it will disable the
frame detector circuit and it will lock on the last byte alignment state.
5