GS1515-CQM Gennum Corporation, GS1515-CQM Datasheet - Page 9

• Manufacturer Part Number: GS1515-CQM
• Description: Hd-linx(tm) HDTV Serial Digital Reclocker
• Manufacturer: Gennum Corporation

During pathological signals, the amount of jitter that the
phase detector will add can be calculated. By choosing the
proper loop bandwidth, the amount of phase detector
induced jitter can also be limited. Typically, for a 1.41MHz
loop bandwidth at 0.2UI input jitter modulation, the phase
detector induced jitter is about 0.015UIp-p. This is not very
significant, even for the pathological signals.
CHARGE PUMP
The charge pump in a slew PLL is different from the charge
pump in a linear PLL. There are two main functions of the
charge pump. One function is to hold the frequency
information of the input data. This information is held by
C
capacitor, C
remove common mode noise. Both C
the same value. The second function of the charge pump is
to provide a binary control voltage to the VCO depending
upon the phase detector output. The output pin, LFA
controls the VCO. Internally there is a 500Ω pull-up resistor,
which is driven with a 100µA current called Ι
analog current Ι
the voltage across the C
The voltage at the LFA node is V
time.
Because of the integrator, Ι
Ι
as often as a clock period. In the locked position, the
average voltage at the LFA (V
that VCO generates frequency ƒ, equal to the data rate
clock frequency. Since Ι
0A and 100µA, there will be two levels generated at the LFA
output.
VCO
The GO1515 is an external hybrid VCO, which has a centre
frequency of 1.485GHz and is also guaranteed to provide
1.485/1.001GHz within the control voltage (3.1V – 4.65V) of
the GS1515 over process, power supply and temperature.
The GO1515 is a very clean frequency source and because
of the internal high Q resonator, it is an order of magnitude
more immune to external noise as compared to on-chip
VCOs.
The VCO gain, Kƒ, is nominally 16MHz/V.
voltage around the average LFA voltage will be 500 x Ι
This will produce two frequencies off from the centre by
ƒ=Kƒ x 500 x Ι
LOOP BANDWIDTH OPTIMIZATION
Since the feed back loop has only digital circuits, the small
signal analysis does not apply to the system. The effective
loop bandwidth scales with the amount of input jitter
modulation index. The following table summarizes the
P
CP1
could change at the positive edge of the data transition
, which is connected between LFS and LFS. The other
CP2
P
/2.
F
between LFS and LFA_GND is used to
, with 5mA maximum drive proportional to
P
CP1
is changing all the time between
F
changes very slowly, whereas
is applied at the same node.
LFA_VCC
LFA_VCC
– 500(Ι
CP1
- 500(Ι
, C
P
CP2
/2+Ι
P
The control
P
+Ι
should be
. Another
F
)) is such
F
) at any
P
/2.
9 of 17
relationship between input jitter modulation index and
bandwidth when R
Typical Application Circuit artwork for the location of R
and C
The product of the input jitter modulation (IJM) and the
bandwidth (BW) is a constant. In this case, it is 282.9kHzUI.
The loop bandwidth automatically reduces with increasing
input jitter, which helps in cleaning up the signal as much
as possible.
Using a series combination of R
an on-chip resistor (as shown in the Typical Application
Circuit) can reduce the loop bandwidth of the GS1515. The
parallel combination of the resistor is directly proportional to
the bandwidth factor. For example, the on-chip 500Ω
resistor yields 282.9kHzUI. If a 50Ω resistor is connected in
parallel, the effective resistance will be (50 || 500) 45.45Ω.
This
[282.9 X (45.45/500)] = 25.72kHzUI. The capacitance C
in series with the R
factor is 50µF. For example, R
C
The synchronous lock time increases with reduced
bandwidth. Nominal synchronous lock time is equal to
[
bandwidth factor (282.9kHzUI) would yield 1.25µs. For
25.72kHzUI,
0.3535/25.72k=13.75µs. Since the C
also charged, it is measured to be about 11µs which is
slightly less than the calculated value of 13.75µs.
The Kƒ of the VCO (GO1515) is specified with a minimum of
11MHz/V and maximum of 21MHz/V which is about ±32%
variation. The 500 x Ι
bandwidth factor would approximately vary by ±45% when
no R
the variability for lower bandwidths will increase by an
additional ±30%.
The C
reduced bandwidths. Smaller C
would result in jitter peaking, lower stability, less probability
of locking but at the same time lowering the asynchronous
0.25
CP3
INPUT JITTER
MODULATION
=1µF.
CP1
×
CP3
CP1
INDEX
resistance
0.05
0.10
0.20
0.50
and C
.
2
and C
/Bandwidth
CP3
the
CP2
are used. Ι
CP1
CP1
yields
P
capacitors should be changed with
/2 will vary about ±10%. The resulting
should be chosen such that the RC
and C
BANDWIDTH
synchronous
factor].
5.657MHz
2.828MHz
1.414MHz
565.7kHz
P
a
CP3
by itself may vary by 30% so
CP1
CP1
are not used.
bandwidth
CP1
That
CP1
and C
=50Ω would require
and C
, C
lock
(jitter modulation x
is,
CP2
CP3
BW JITTER
282.9kHzUI
282.9kHzUI
282.9kHzUI
282.9kHzUI
CP2
FACTOR
and C
in parallel to
the
BW)
factor
capacitors
522 - 23 - 03
time
See the
CP3
default
are
CP1
CP3
of
is