RC28F256 Intel Corporation, RC28F256 Datasheet - Page 57

• Manufacturer Part Number: RC28F256
• Description: Intel StrataFlash Embedded Memory
• Manufacturer: Intel Corporation

www.DataSheet4U.com
Figure 29.
10.3.3
10.3.3.1
Datasheet
A[MAX:0]
D[15:0]
ADV#
CLK
CE#
Example Latency Count Setting using Code 3
WAIT Polarity
The WAIT Polarity bit (WP), RCR[10] determines the asserted level (V
When WP is set, WAIT is asserted high (default). When WP is cleared, WAIT is asserted low.
WAIT changes state on valid clock edges during active bus cycles (CE# asserted, OE# asserted,
RST# deasserted).
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR[15]=0). The WAIT signal is only “deasserted” when data is valid on the bus.
When the device is operating in synchronous non-array read mode, such as read status, read ID, or
read query. The WAIT signal is also “deasserted” when data is valid on the bus.
WAIT behavior during synchronous non-array reads at the end of word line works correctly only
on the first data access.
When the device is operating in asynchronous page mode, asynchronous single word read mode,
and all write operations, WAIT is set to a deasserted state as determined by RCR[10]. See
17, “Asynchronous Single-Word Read (ADV# Latch)” on page
Page-Mode Read Timing” on page
Intel StrataFlash
Order Number: 306666, Revision: 001
0
Code 3
®
39.
Embedded Memory (P30)
1
High-Z
R103
Address
2
38, and
3
OH
Figure 18, “Asynchronous
t
or V
Data
Data
1-Gbit P30 Family
OL
4
) of WAIT.
April 2005
Figure
57