MB86330 Fujitsu Media Devices Limited, MB86330 Datasheet - Page 20

• Manufacturer Part Number: MB86330
• Description: 16-bit Fixed-point DSP
• Manufacturer: Fujitsu Media Devices Limited

20
MB86330
Bit abbreviation
(1) Status Register
DETAILED DESCRIPTION OF SPECIAL REGISTERS
MDMA
bit 15
RND
INT0
INT1
INT2
OV1
OV3
ITG
CP
IT
V1
V2
V3
IT
C
Z
N
bit 14
OV3
bit 13
OV1
Carry flag
Zero flag
Negative flag
Overflow flag 1
Overflow flag 2
Overflow flag 3
Operating mode
specification flag
Rounding mode setup
Clip flag
DMA enable flag
Interrupt enable flag
Interrupt enable flag
Interrupt enable flag
V1 interrupt enable flag
V3 interrupt enable flag
Interrupt enable flag
bit 12
INT2
Bit name
bit 11
INT1
bit 10
INT0 MDMA
bit 9
Reset when no carry occurs.
Not changed by transfer instruction execution.
Set when the operation result is 0.
Reset when the operation result is not 0.
Not changed by transfer instruction execution.
Set when the operation result is smaller than 0.
Reset when the operation result is equal to or greater than 0.
Not changed by transfer instruction execution.
Set when the operation result overflows.
Reset when the operation result does not overflow.
Not changed by transfer instruction execution.
Set when the operation result overflows.
Set V2 is reset only by hardware or by ST programming by the
transfer instruction.
Not changed by transfer instruction execution.
Set when the operation result of an instruction stored in CX or DX
cannot be expressed by 32 bits (but by 40 bits).
Reset when the operation result can be expressed by 32 bits.
Specify this when executing multiplication in integral mode.
Used to set ON/OFF of rounding processing when data is
transferred from a register consisting of 32 or more bits to a 16-bit
register.
when overflow occurs during the operation.
0: Disabled, 1: Enabled
0: Disabled, 1: Enabled
0: Disabled, 1: Enabled
Operation overflow interrupt enable flag. An interrupt is generated
when V1 is set.
0: An interrupt is disabled. 1: An interrupt is enabled.
Operation overflow interrupt enable flag. An interrupt is generated
when V3 is set.
0: An interrupt is disabled. 1: An interrupt is enabled.
OV1, OV3 and INT0 to INT7 interrupt enable flag
0: An interrupt is disabled. 1: An interrupt is enabled.
Set when carry occurs as a result of operation execution.
Used to specify whether the operation result is to be clipped
Enables a DMA interrupt. (0: Disabled)
INT0 (SMODE) interrupt enable flag
INT1 interrupt enable flag
INT2 interrupt enable flag
bit 8
CP
RND
bit 7
bit 6
ITG
bit 5
V3
Description
bit 4
V2
bit 3
V1
bit 2
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N
bit 1
Z
bit 0
C