MB86291A Fujitsu Media Devices Limited, MB86291A Datasheet - Page 8

• Manufacturer Part Number: MB86291A
• Description: Graphics Display Controller
• Manufacturer: Fujitsu Media Devices Limited

8
MB86291A
Note : The video capture interface inputs digital video signals in the ITU-RBT-656 format.
*1 : Do not connect anything.
*2 : Input the “H” level.
Notes :
Note : Use the CLKSEL pin to select the input clock frequency for using the internal PLL with CKM
Note : Immediately after turning the power supply on, input a pulse whose low level period is 500 ns or more to the
CLKSEL1, CLKSEL0
Video Capture Interface
Clock Input
Pin Name
OSCOUT*
OSCCNT*
VI0-VI7
Pin Name
S pin before setting it to high level. After the S signal goes high, input the RESET signal at low level for 300
CCLK
s or more
CKM
CLK
operating clock and display dot clock. Usually input 4 Fsc ( 14.31818 MHz) . The internal PLL generates
the internal operating clock signal of 100 MHz and the display reference clock signal of 200 MHz.
generated by the internal PLL and the bus clock BCLKI input to the host CPU interface. Select the BCLKI
input to use the host CPU bus at 100 MHz.
The clock input block inputs the clock signal that serves as the basis for the reference clock for the internal
The internal operating clock signal to be used can be selected between the clock signal (100 MHz)
CLKSEL1
S
H
H
L
L
2
1
CKM
H
L
Input/output
Input/output
Input/output
Input
Input
CLKSEL0
Input
Input
Input
Input
Input
H
H
L
L
Select internal PLL output.
Select host CPU bus clock (BCLKI)
Clock input signal
PLL reset signal
Clock mode signal
Clock rate select signal
For connection of crystal oscillator (Reserved)
For selection of crystal oscillator (Reserved)
Digital video input clock signal input
Digital video data input
Input 13.5 MHz.
Input 14.32 MHz.
Input 17.73 MHz.
Reserved
Clock Frequency
Clock Mode
Function
Function
w w w . D a t a S h e e t
L.