CT2566 Aeroflex Circuit Technology, CT2566 Datasheet - Page 12

• Manufacturer Part Number: CT2566
• Description: CT2566 MIL-STD-1553 to Microprocessor Interface Unit
• Manufacturer: Aeroflex Circuit Technology

MEM/REG and the A2 bit to logic "0" (See Table 2).
External registers are selected by asserting MEM/REG
logic "0" and A2 bit to a logic "1". The signals EXTEN
and EXTLD are used to read and write from the
external registers (See Figures 26 to 28).
register used to define the 1553 operating mode (BC,
MT, or RTU) and the associated RTU status bits. The
four MSBs define the mode of operation; the four LSBs
define the RTU status bits (See Figure 8).
will be present on the respective CT2566 output pins to
the 1553 device. The MT bit is inverted at the output.
CPU must issue a Controller Start Command (See
Figure 14). This is done by setting bit 1 of the
Start/Reset Register to a logic "1". An EOM interrupt
will be generated each time a message transfer has
been completed. A BCEOM will be generated once the
specified number of messages has been transferred
(message counter = FFFF).
at the end of a message if a timeout condition or error
condition was detected. If the STOP ON ERROR bit in
the Configuration Register is set, the CT2566 will stop
bus transactions until a new Controller Start command
is issued by the CPU. These interrupts may be masked
by the CPU through the Interrupt Mask Register.
Start/Reset Register, the CT2566 takes the following
actions:
memory by the associated 1553 interface unit using the
internal Address Register.
the 1553 interface unit issues an EOM pulse to the
CT2566 which takes the following actions:
Aeroflex Circuit Technology
Configuration Register
BC START SEQUENCE
BC EOM Sequence.
The CPU selects an internal register by asserting
The Configuration Register is an eight bit read/write
All bits in the Configuration Register (except bit 12)
To begin transferring messages onto the bus, the
A Format Error Status Set Interrupt will be generated
After setting the CONTROLLER START bit in the
Note that data words are transferred to an from
Upon completion of a 1553 message (valid or invalid)
1. Reads the Stack Pointer to get the address of the
2. Stores an SOM flag in the Block Status Word to
3. Stores the Time Tag if used.
4. Reads the Data Block Address from the fourth
5. Issues a BCSTART pulse to the associated 1553
current Descriptor Stack Entry.
indicate a transfer operation is in progress.
location of the Descriptor Stack and transfers the
Data Block Address into an internal Address
Register.
device to start the message transfers.
12
Note: When the BC expects the BROADCAST bit set in the status
15
1. Reads the Stack Pointer to get the address of the
MASK BROADCAST BIT
current Descriptor Stack Entry.
BC Initialization (under user control)
word, a logic "1" will mask the status interrupt error flag. A
FORMAT error will be generated if the MASK BROADCAST bit
is not set.
BUS CHANNEL A/B
NOT USED
Figure 13 – BC Control Word
BROADCAST
MODE CODE
RTU TO RTU
NOT USED
NOT USED
INITIALIZE STACK POINTER
LOAD MESSAGE COUNTER
LOCATION OF STACK WITH
ISSUE RESET COMMAND
ISSUE START COMMAND
RESISTER TO BC MODE
INITIALIZE INTERRUPT
LOAD EVERY FOURTH
SCDCT2566 REV B 8/10/99 Plainview NY [phone]
SET CONFIGURATION
STARTING ADDRESS
LOAD MESSAGES
MASK REGISTER
Figure 11
8
START
7
0