FM25CL64B Ramtron, FM25CL64B Datasheet - Page 8

• Manufacturer Part Number: FM25CL64B
• Description: 3V F-RAM Memory
• Manufacturer: Ramtron

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SCK
Endurance
The FM25CL64B devices are capable of being
accessed at least 10
RAM memory operates with a read and restore
mechanism. Therefore, an endurance cycle is applied
on a row basis for each access (read or write) to the
memory array. The F-RAM architecture is based on
an array of rows and columns. Rows are defined by
A12-A3 and column addresses by A2-A0. See Block
Diagram (pg 2) which shows the array as 1K rows of
Rev. 1.2
Feb. 2011
SO
CS
SCK
SI
CS
SO
SI
0
0
0
0
0
1
0
1
0
2
0
14
2
op-code
0
3
times, reads or writes. An F-
op-code
0
Table 5. Time to Reach Endurance Limit for Repeating 64-byte Loop
3
0
4
SCK Freq
0
4
(MHz)
0
5
0
20
10
5
5
1
6
Figure 9. Memory Write (WREN not shown)
1
6
0
7
1
MSB
7
MSB
X
0
X
0
X
1
Endurance
Cycles/sec.
Figure 10. Memory Read
X
1
37,310
18,660
X 12 11 10
9,330
2
X 12 11 10
13-bit Address
2
3
13-bit Address
3
4
4
5
5
64-bits each. The entire row is internally accessed
once whether a single byte or all eight bytes are read
or written. Each byte in the row is counted only once
in an endurance calculation. The table below shows
endurance calculations for 64-byte repeating loop,
which includes an op-code, a starting address, and a
sequential 64-byte data stream. This causes each byte
to experience one endurance cycle through the loop.
F-RAM read and write endurance is virtually
unlimited even at 20MHz clock rate.
Cycles/year
Endurance
1.18 x 10
5.88 x 10
2.94 x 10
4
3
4
3
3
4
3
4
2
5
12
11
11
2
5
1
6
FM25CL64B - 64Kb 3V SPI F-RAM
LSB MSB
1
6
0
7
LSB MSB
Years to Reach
0
7
7
0
7
0
Limit
170.2
340.3
6
85.1
1
6
1
5
2
Data
5
2
4
3
Data
4
3
3
4
3
4
2
5
2
5
1
6
Page 8 of 14
1
6
LSB
0
7
LSB
0
7
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