CS6310 Amphion, CS6310 Datasheet - Page 4

• Manufacturer Part Number: CS6310
• Description: Forward DCT (Encoder)
• Manufacturer: Amphion

dimensional computation stages of 2D-DCT. The output from
the first stage is stored in the Transpose Memory and
appropriately supplied to the second stage. Once the complete
8x8 block has been processed, the PixRdy signal is asserted to
indicate that the core can now read the next block of data. The
start of each output block is indicated by the assertion of
DctDcOut signal which coincides with the first output sample
at the Dct port.
There is a latency of 75 clock cycles before which the first
output sample appears at the output. Consequently, there is a
similar latency of 75 clock cycles between the last input data
and the last output data. The latency is depicted in the
functional timing diagram in Figure 4.
Figure 4: DCT Timing
4
CLK
PixIn
PixStrb
PixRdy
DctDcOut
Q
CS6310
I/O FUNCTIONAL TIMING DIAGRAMS
LATENCY IN THE DESIGN
63
0
1
High Performance DCT
2
3
System Latency
63
0
1
2
The timing diagram in Figure 4 depicts the activities at
various ports for DCT operation. The start of the block is
marked by PixStrb pulse which remains active for one clock
period. After 75 clock cycles, i.e. system latency, the DctDcOut
goes high to mark the start of new output data block at Q port.
The processing of two contiguous input blocks can be delayed
by delaying the assertion of PixStrb signal. The PixRdy signal,
which shows that the core is ready for processing, will remain
asserted until the core starts to read new data block. The core
will start processing the data when PixStrb is asserted. All
input signals are sampled with CLK and all outputs are
updated with CLK. Any gaps at the input PixIn are replicated
at the output Q port after the latent period. The core is capable
of performing consecutive DCT with or without gaps between
successive input blocks.
11
0
12
1
2
63
11
0
12
1
63