CD2231 Intel Corporation, CD2231 Datasheet - Page 140
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CD2231
Manufacturer Part Number
CD2231
Description
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
Manufacturer
Intel Corporation
Datasheet
1.CD2231.pdf
(178 pages)
- Current page: 140 of 178
- Download datasheet (3Mb)
CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
8.6.2
8.6.3
140
Register Name: BERCNT
Register Description: Bus Error Retry Count
Default Value: x’00
Access: Byte Read/Write
Register Name: DMABSTS
Register Description: DMA Buffer Status
Default Value: x’00
Access: Byte Read only
TDAlign
Bit 7
Bit 7
Bit 3
Bits 2:0
Bus Error Retry Count (BERCNT)
When this register is programmed to zero, any bus error causes a receive/transmit interrupt to be
generated and DMA operations suspended to the buffer in error, until the interrupt is processed by
the host CPU.
When this register contains a non-zero value and when a bus error occurs, the CD2231 retries the
same DMA operation and decrements the register value by one. When the value reaches zero, the
next bus error causes an interrupt, at that time a new count can be loaded by the host CPU.
DMA Buffer Status (DMABSTS)
When CD2231 requires an external buffer for DMA transfer, it checks Ntbuf/Nrbuf bits to decide
which buffer to use. Once the CD2231 starts using the buffer, it toggles Ntbuf/Nrbuf bits, and sets
Tbusy/Rbusy bits. Ntbuf and Nrbuf bits are set to Buffer A at system initialization.
Bit 7
Bit 6
Bit 5
Bit 4
RstApd
Bit 6
Bit 6
Byte DMA
0 = The CD2231 attempts to perform 16-bit data transfers whenever possible, and 8-
bit data transfers only when necessary (when only one byte is available or there are
odd address boundaries).
1 = The CD2231 always performs 8-bit DMA transfers, the position of the data on
the bus still follows the normal rules relating to the BYTESWAP pin.
Reserved – must be ‘0’.
This status bit is used internally to manage data alignment in the transmit FIFO.
Reset Append mode is set after the terminate append buffer command in STCR has
been recognized, and is cleared after the remaining data has been flushed from the
buffer.
Current transmit buffer is used internally to mark the actual buffer in use.
Append (only Buffer A can be used as an append buffer)
Transmit append buffer usage indicator
CrtBuf
Bit 5
Bit 5
Append
Bit 4
Bit 4
Binary value
Ntbuf
Bit 3
Bit 3
Tbusy
Bit 2
Bit 2
Motorola Hex Address: x’8E
Motorola Hex Address: x’19
Bit 1
Nrbuf
Bit 1
Intel Hex Address: x’8D
Intel Hex Address: x’1A
Datasheet
Rbusy
Bit 0
Bit 0
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