CS3710 Amphion, CS3710 Datasheet - Page 2

• Manufacturer Part Number: CS3710
• Description: 32 Qam Modulator
• Manufacturer: Amphion

Table 1 describes the input and output ports (shown
graphically in Figure 2) of the CS3710 modular core. Unless
otherwise stated, all signals are active high and bit(0) is the
least significant bit.
The internal architecture of the Core is illustrated in Figure 3.
It comprises spectral error protection, synch insertion and
channel coding circuitry. The core is controlled by a bank of
registers accessed through a microprocessor interface.
Figure 3: Block Diagram of the CS3710
2
GENERAL I/OS
CLK
RESET
MODULATOR USER INPUT
TXDATA[7:0]
TXUSRCLK
TXSYNC
MODULATOR CONTROL PIN
TXRX
PRBS
SSBEnab
BPTCM
CS3710
Input
Data
INPUT/OUTPUT DESCRIPTION
Name
PRBS
Table 1: CS3710 32 QAM Modulator Interface Signal Descriptions
32 QAM Modulator
Synchro-
nization
I/O
I
I
I
I
I
I
I
I
I
Scrambler
Clock at 2 x Symbol Rate
Active low asynchronous reset signal – applied to all registers
Byte wide data input
Byte clock input – rising edge active
Indicates first byte in Frame – asserted during the TXUSRCLK cycle before the
first byte of a frame is on the TXDATA port
Input data selector: 1: TXDATA or PRBS;
Pseudo Random Binary Sequence generator enable signal, TXRX=1 and
PRBS=1 enable PRBS sequence
High to enable SSB (Single Side Band) stream
High to by pass TCM (Trellis Code Modulator) encoder
Control Register Bank
Encoder
RS
Insertion
Unique
Word
0: RXDATA
Figure 2: CS3710 Symbol
leaver
Inter-
TXDATA[7:0]
TXSYNC
RXDATA[7:0]
RXSYNC
TXUSRCLK
CLK
RESET
TXRX
PRBS
SSBEnab
BPTCM
TWOSCOM
Description
TCM
32-QAM modulator
CS3710
SSB
Map
TXQ_OUT[9:0]
TXI_OUT[9:0]
SRRC
TCM_Q[4:0]
filter
TCM_I[4:0]
TCM_Valid
TXEMPTY
TX_Valid
TXFULL
Output