M50FLW040B ST Microelectronics, M50FLW040B Datasheet - Page 24

• Manufacturer Part Number: M50FLW040B
• Description: 4 Mbit 3V Supply Firmware Hub / Low Pin Count Flash Memory
• Manufacturer: ST Microelectronics

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M50FLW040A, M50FLW040B
FIRMWARE HUB/LOW PIN COUNT (FWH/LPC) INTERFACE CONFIGURATION
REGISTERS
When the Firmware Hub Interface/Low Pin Count
is selected, several additional registers can be ac-
cessed. These registers control the protection sta-
tus of the Blocks, read the General Purpose Input
pins and identify the memory using the manufac-
turer code. See
the Configuration Registers. The Configuration
registers are accessed directly without using any
specific command code. A single Bus Write or Bus
Read Operation, with the appropriate address (in-
cluding A22=0), is all that is needed.
Lock Registers
The Lock Registers control the protection status of
the Blocks. Each Block has its own Lock Register.
Three bits within each Lock Register control the
protection of each block: the Write Lock Bit, the
Read Lock Bit and the Lock Down Bit.
The Lock Registers can be read and written. Care
should be taken, though, when writing. Once the
Lock Down Bit is set, ‘1’, further modifications to
the Lock Register cannot be made until it is
cleared again by a reset or power-up.
See
the Lock Registers.
Write Lock. The Write Lock Bit determines
whether the contents of the Block can be modified
(using the Program or Erase Command). When
the Write Lock Bit is set, ‘1’, the block is write pro-
tected – any operations that attempt to change the
data in the block will fail, and the Status Register
will report the error. When the Write Lock Bit is re-
Table 15. Configuration Register Map
Note: In LPC mode, a most significant nibble, F, must be added to the memory address. For all registers, A22=0, and the remaining address
24/52
Lock Registers (For details, see
MANU_REG
Mnemonic
GPI_REG
Table 16.
bits should be set according to the rules shown in the ADDR field of
for details on the bit definitions of
Table 15.
Firmware Hub/Low Pin Count (FWH/LPC) General
Purpose Input Register
Manufacturer Code Register
for the memory map of
APPENDIX
Register Name
A.)
set, ‘0’, the block is not write protected by the Lock
Register, and may be modified, unless it is write
protected by some other means.
If the Top Block Lock signal, TBL, is Low, V
the Top Block (Block 7) is write protected, and
cannot be modified. Similarly, if the Write Protect
signal, WP, is Low, V
(Blocks 0 to 6) are write protected, and cannot be
modified.
After power-up, or reset, the Write Lock Bit is al-
ways set to ‘1’ (write-protected).
Read Lock. The Read Lock bit determines
whether the contents of the Block can be read (in
Read mode). When the Read Lock Bit is set, ‘1’,
the block is read protected – any operation that at-
tempts to read the contents of the block will read
00h instead. When the Read Lock Bit is reset, ‘0’,
read operations are allowed in the Block, and re-
turn the value of the data that had been pro-
grammed in the block.
After power-up, or reset, the Read Lock Bit is al-
ways reset to ‘0’ (not read-protected).
Lock Down. The Lock Down Bit provides a
mechanism for protecting software data from sim-
ple hacking and malicious attack. When the Lock
Down Bit is set, ‘1’, further modification to the
Write Lock, Read Lock and Lock Down Bits cannot
be performed. A reset, or power-up, is required be-
fore changes to these bits can be made. When the
Lock Down Bit is reset, ‘0’, the Write Lock, Read
Lock and Lock Down Bits can be changed.
Table 6.
to
Table
9..
FBC0100h
FBC0000h
Address
Memory
IL
, then the Main Blocks
Default
Value
N/A
20h
Access
IL
R
R
, then