PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 92

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PI7C9X110

Manufacturer Part Number
PI7C9X110
Description
Pcie-to-pci Reversible Bridge
Manufacturer
Pericom Semiconductor Corporation
Datasheet

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0
Pericom Semiconductor
BIT
31:12
FUNCTION
Base Address
RW/RO
TYPE
Page 92 of 145
DESCRIPTION
The size and type of this Base Address Register are defined from Upstream
Memory 3 Setup Register (CSR Offset 034h), which can be initialized by
EEPROM (I2C) or SM Bus or Local Processor. Writing a zero to bit [31] of
the setup registers (CSR Offset 034h and 038h) to disable this register. The
range of this register is from 4KB to 9EB for memory space. PI7C9X110
uses this register and the Upstream Memory 3 Upper Base Address Register
when 64-bit addressing programmed (bit [21] of Offset 68h). When 64-bit
addressing is disabled, no address translation is performed. All 64-bit
address transactions on the secondary interface falling outside of the
Downstream Memory 3 address range are forwarded upstream.
Reset to 00000h
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110

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