SCANSTA101 National Semiconductor Corporation, SCANSTA101 Datasheet - Page 17

• Manufacturer Part Number: SCANSTA101
• Description: Low Voltage Ieee 1149.1 Sta Master
• Manufacturer: National Semiconductor Corporation

MODE REGISTER WRITE TO VECTOR/SEQUENCER START
Figure 7 shows the timing from the processor write to the start
of vector processing, whereas Figure 8 shows the timing from
the processor write to the start of sequencer processing. A
processor write to the Start registers is indicated by a "new
data" pulse. On the same SCK rising edge when the "new
data" is detected to be high, the Start or Setup register con-
tents will be updated with new data. So, the decoding of the
enables takes place during the next clock cycle to determine
whether to process the sequencer or a vector. Therefore, one
clock after the "new data" is detected, the SSIC starts loading
the pointer register on consecutive cycles with the appropriate
addresses to fetch the Sequencer, Vector and Macro Struc-
tures. Once the headers are decoded and Structure Control
Registers are set up, the SSIC loads the pointer register so
that data from the TDO_SM memory area is fetched and
loaded into the TDO_SM shifter before being shifted out.
9.
1.
2.
3.
If the Sync Bit Support Enable is set, fetch sync bit
count, set the count length, and drive the TDO_SM
high until sync bit count is one and while TMS_SM
remains set to the loop bit.
If the TAP tracker is in the Shift-IR state and the
number of levels of hierarchy is greater than
one, set the count length to eight, and drive
TDO_SM with post-PAD bits (all high) until the
count length is zero for each level of hierarchy
and while TMS_SM remains set to the loop bit.
If the TAP tracker is in the Shift-DR state and
the number of levels of hierarchy is greater than
one, drive TDO_SM with a post-PAD bit (high)
for each level of hierarchy and while TMS_SM
remains set to the loop bit.
For the final level of hierarchy or if there is only
one level of hierarchy, and if the TAP tracker is
in the Shift-IR state, set the count length to
eight, and drive TDO_SM with post-PAD bits (all
high) until the count length is one and while
TMS_SM remains set to the loop bit.
FIGURE 7. Timing from Mode Register Write to Vector Start
17
10. If the Post-shift TCK_SM Count is not zero, then enable
11. If the Sequencer is being used,
12. If the Vector is being used return to the Idle state.
However if there are any sync bits and/or header bits and/or
ScanBridge support is enabled, then the sync bits and/or
header bits and/or ScanBridge pre-PAD bits will be loaded
into the TDO_SM shifter before processing the actual test
vector. Once the actual test vector is completely shifted out,
again depending on the ScanBridge support and/or the use
of trailers, post-PAD bits and the trailer bits are loaded and
shifted out through the TDO_SM shifter.
The count length will be decremented by one with each shift.
After shifting out all the current shifter contents the shifter will
be loaded with new data before the falling edge of the next
TCK_SM, if the count length is not exhausted. In the case
where data cannot be loaded from the memory before the
next falling edge of TCK_SM, the TCK_SM will be gated until
the data is available.
10. Set TMS_SM to the bit 8 of the TMS_SM Macro
TCK_SM and drive TMS_SM using the last seven bits of
the macro until the Post-shift TCK_SM Count is zero.
1.
2.
3.
Structure sequence and drive TDO_SM with the
final vector bit or trailer bit or post-PAD bit or sync
bit. After shifting out the final vector bit, disable the
comparator and register the comparison results.
Decrement the sequence repeat count and return to
Step 3c if the Compare or Mask/Compare is enabled
and the results of compare is a fail.
Decrement the vector repeat count and return to
Step 3e if the if the Compare or Mask/Compare is
enabled and the results of compare is a pass.
Decrement the vector repeat count and return to
Step 3e if the Compare or Mask/ Compare is not
enabled.
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