MBM29DL32XTE Fujitsu Microelectronics, Inc., MBM29DL32XTE Datasheet - Page 47

• Manufacturer Part Number: MBM29DL32XTE
• Description: Flash Memory 32m 4m X 8/2m X 16 Bit Dual Operation
• Manufacturer: Fujitsu Microelectronics, Inc.

• Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29DL32XTE/BE devices. When
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ
to DQ
becomes the lowest address bit and DQ
an 8-bit operation and hence commands are written at DQ
to Figures 15, 16 and 17 for the timing diagram.
• Data Protection
The MBM29DL32XTE/BE are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices automat-
ically reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of
the memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form V
and power-down transitions or system noise.
• Low V
To avoid initiation of a write cycle during V
than V
disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the
V
prevent unintentional writes when V
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
• Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
• Logical Inhibit
Writing is inhibited by holding any one of OE = V
must be a logical zero while OE is a logical one.
• Power-Up Write Inhibit
Power-up of the devices with WE = CE = V
The internal state machine is automatically reset to the read mode on power-up.
CC
level is greater than V
15
LKO
. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ
CC
(Min.). If V
Write Inhibit
CC
< V
LKO
LKO
. It is the users responsibility to ensure that the control pins are logically correct to
, the command register is disabled and all internal program/erase circuits are
CC
is above V
8
to DQ
CC
IL
and OE = V
power-up and power-down, a write cycle is locked out for V
14
LKO
IL
bits are tri-stated. However, the command bus cycle is always
, CE = V
(Min.).
MBM29DL32XTE/BE
IH
0
will not accept commands on the rising edge of WE.
IH
to DQ
, or WE = V
7
and the DQ
IH
. To initiate a write cycle CE and WE
8
to DQ
15
bits are ignored. Refer
CC
-80/90/12
power-up
15
/A
CC
-1
less
pin
0
47