MTV212M64 ETC-unknow, MTV212M64 Datasheet
MTV212M64
Related parts for MTV212M64
MTV212M64 Summary of contents
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... BLOCK DIAGRAM This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product. Revision 1.2 MTP Type - 1 - MTV212M64 (Rev. 1.2) 2000/07/04 ...
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... MTV212A48U 768 MTV212A64U 1024 Remark: The major pin connection differences between USB (MTV212M64U) and non-USB (MTV212M64) types are pin and #6 for SDIP42 and PLCC44. The pin name of USB device is V33CAP(#4), VM(#5) and VP(#6), while NC (No Connection) for non-USB device. Revision 1.2 ROM RAM ...
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... HBLANK/P4.1 VSS 10 VBLANK/P4 DA7/HCLAMP X1 12 DA6/P5.6 ISDA/P3.4/T0 13 P2.6/DA12 ISCL/P3.5/T1 14 P2.5/DA11 STOUT/P4.2 15 P2.4/DA10 P2.2/AD2 16 HSCL/P3.0/Rxd P1.0 17 HSDA/P3.1/Txd P2.0/AD0 P2.1/AD1 P1.7 P1.6 P1 MTV212M64 (Rev. 1. VSYNC 2 39 HSYNC 3 38 DA3/P5 DA4/P5 DA5/P5 DA8/HALFH RST 7 34 DA9/HALFV VDD 8 33 HBLANK/P4.1 MTV212M ...
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... PWM DAC output / Hsync half freq. output (open drain PWM DAC output / General purpose I/O (open drain PWM DAC output / General purpose I/O (open drain PWM DAC output / General purpose I/O (open drain Horizontal SYNC or Composite SYNC Input Vertical SYNC input MTV212M64 (Rev. 1.2) Description 2000/07/04 ...
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... XBANK register. Program can initialize Ri value and use "MOVX" instruction to access the AUXRAM. FFh Internal RAM SFR Accessible by Accessible by indirect direct addressing addressing only (Using MOV A,@Ri instruction) 80h 7Fh Internal RAM Accessible by direct and indirect addressing 00h Revision 1.2 MTV212M64 - 5 - (Rev. 1.2) 2000/07/04 ...
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... DA12E DA11E DA10E AD3E P56E P55E P54E P53E IIICE HLFVE HLFHE HCLPE DIV253 FclkE IICpass ENSCL - 6 - MTV212M64 (Rev. 1.2) AUXRAM AUXRAM Accessible by Accessible by indirect external indirect external RAM addressing RAM addressing (XBANK=4)(Using (XBANK=5)(Using MOVX A,@Ri MOVX A,@Ri instruction) instruction) bit2 bit1 ...
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... Master IIC frequency. select 200KHz Master IIC frequency. select 50KHz Master IIC frequency. select 100KHz Master IIC frequency. 5-bits slave address. 6-bits slave address. 7-bits slave address. Select AUXRAM bank 0. Select AUXRAM bank 1. Select AUXRAM bank 2. Select AUXRAM bank MTV212M64 (Rev. 1.2) 2000/07/04 ...
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... Pulse width of PWM DAC 6 Pulse width of PWM DAC 7 Pulse width of PWM DAC 8 Pulse width of PWM DAC 9 Pulse width of PWM DAC 10 Pulse width of PWM DAC 11 Pulse width of PWM DAC 12 Pulse width of PWM DAC MTV212M64 (Rev. 1.2) bit2 bit1 bit0 P42 P41 P40 P52 ...
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... Polarity Check & Vpol Freq. Count XOR CVSYNC Vself Present CVpre Check Polarity Check & Hpol Sync Seperator Hpre Present Check & Hfreq Freq. Count Composite Pulse Insert XOR Hself H/V SYNC Processor Block Diagram - 9 - MTV212M64 (Rev. 1.2) Vbpl XOR VBLANK Hbpl XOR HBLANK 2000/07/04 ...
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... The VBLANK output frequency of the pattern is 60Hz originally designed to support monitor manufacturer to do burn-in test, or offer end-user a reference to check the monitor. The generator's output STOUT shares the output pin with P4.2. Revision 1.2 892 868 833 735 - 10 - MTV212M64 (Rev. 1.2) 2000/07/04 ...
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... MYSON TECHNOLOGY Display Region Positive cross-hatch Full white Revision 1.2 MTV212M64 Negative cross-hatch Full black - 11 - (Rev. 1.2) 2000/07/04 ...
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... HF4 HF3 VF11 VF6 VF5 VF4 VF3 C0 NoHins Selft STF1 STF0 CLPEG CLPPO CLPW2 CLPW1 CLPW0 HFchg EVPR EHPL EVPL EHF - 12 - MTV212M64 (Rev. 1.2) 31.7KHz, 60Hz Absolute time H dots 31.5us 640 24.05us 488.6 12 0.45us 9 90 3us 61 4us 81.27 Absolute time V lines 16.663ms 480 15 ...
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... Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt enable bit is set, the 8051 core's INT1 source will be driven by a zero level. Software MUST clear this register while serve the interrupt routine. Revision 1.2 63.5KHz(horizontal) output selected. 47.6KHz(horizontal) output selected. 31.75KHz(horizontal) output selected MTV212M64 (Rev. 1.2) 2000/07/04 ...
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... IIC block A will respond to slave address 10100xxb and save the 2 LSB "xx" in XFR. This feature enables MTV212M to meet PC99 requirement. The MTV212M will return to DDC1 mode if HSCL is kept high for 128 VSYNC clock period. However, it will Revision 1.2 MTV212M64 - 14 - (Rev. 1.2) 2000/07/04 ...
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... Read out MBUF the useless byte to continue the data transfer. 6. After the MTV212M receives a new byte, the MbufI interrupt is triggered again. 7. Read MBUF also trigger the next receive operation, but set P bit before read can terminate the operation. Revision 1.2 MTV212M64 - 15 - (Rev. 1.2) 2000/07/04 ...
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... Master IIC receive/transmit data buffer Slave A IIC receive buffer Slave A IIC transmit buffer Slave A IIC address Slave B IIC receive buffer Slave B IIC transmit buffer Slave B IIC address DDC1 transmit data buffer - 16 - MTV212M64 (Rev. 1.2) bit2 bit1 bit0 MAckO P S SlvAlsb1 SlvAlsb0 SlvAMI ...
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... The WatchDog Timer automatically generates a device reset when it is overflow. The interval of overflow is 0.25 sec x N, where number from and can be programmed via register WDT(2:0). The timer function is disabled after power on reset, user can activate this function by setting WEN, and clear the timer by set WCLR. Revision 1.2 MTV212M64 - 17 - (Rev. 1.2) 2000/07/04 ...
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... Enable ADC. Select ADC0 pin input. Select ADC1 pin input. Select ADC2 pin input. Select ADC3 pin input MTV212M64 (Rev. 1.2) bit2 bit1 bit0 SADC2 SADC1 SADC0 WDT2 WDT1 ...
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... S/W can keep the RsmI alive before enter the suspend mode. Reg name addr bit7 USBADR 60h (r/w) ENUSB INTFLG 61h (r/w) USBrstI INTEN 62h (w) EUrstI EP0STUS 63h (r) RC0tgl Revision 1.2 bit6 bit5 bit4 bit3 USBadr RC0I TX1I TX0I RsmI ERC0I ETX1I ETX0I ERsmI RC0err EP0dir EP0set - 19 - MTV212M64 (Rev. 1.2) bit2 bit1 bit0 RC0cnt 2000/07/04 ...
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... Endpoint 1 transmit FIFO 2nd byte Endpoint 1 transmit FIFO 3rd byte Endpoint 1 transmit FIFO 4th byte Endpoint 1 transmit FIFO 5th byte Endpoint 1 transmit FIFO 6th byte Endpoint 1 transmit FIFO 7th byte Endpoint 1 transmit FIFO 8th byte - 20 - MTV212M64 (Rev. 1.2) USBactv TX0cnt TX1cnt 2000/07/04 ...
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... Endpoint 1 will transmit DATA1 packet Endpoint 1 will transmit DATA0 packet. EP1stall = 1 Endpoint 1 will stall IN packet. TX1cnt : Endpoint 1 transmit byte count, write only. RC0FIFO (r) : Endpoint 0 receive FIFO registers. TX0FIFO (w) : Endpoint 0 transmit FIFO registers. TX1FIFO (w) : Endpoint 1 transmit FIFO registers. Revision 1.2 MTV212M64 - 21 - (Rev. 1.2) 2000/07/04 ...
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... HF4 HF3 VF11 VF6 VF5 VF4 VF3 C0 NoHins Selft STF1 STF0 CLPEG CLPPO CLPW2 CLPW1 CLPW0 HFchg EVPR EHPL EVPL EHF - 22 - MTV212M64 (Rev. 1.2) bit2 bit1 bit0 MAckO P S SlvAlsb1 SlvAlsb0 SlvAMI DbufI MbufI SlvAMI MbufI EMbufI SADC2 SADC1 SADC0 WDT2 WDT1 ...
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... Endpoint 1 transmit FIFO 2nd byte Endpoint 1 transmit FIFO 3rd byte Endpoint 1 transmit FIFO 4th byte Endpoint 1 transmit FIFO 5th byte Endpoint 1 transmit FIFO 6th byte Endpoint 1 transmit FIFO 7th byte Endpoint 1 transmit FIFO 8th byte - 23 - MTV212M64 (Rev. 1.2) RC0cnt USBactv TX0cnt TX1cnt 2000/07/04 ...
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... Idd Idle Power-Down Rrst VDD=5V 50 Cio Symbol Condition Min. fXtal fDA fXtal=12MHz 46.875 tHIPW fXtal=12MHz 0.3 tVIPW fXtal=12MHz 3 tHHBJ tVVBD fXtal=12MHz tVCPW FXtal=12MHz 20 tDCSU 200 - 24 - MTV212M64 (Rev. 1.2) Unit Max. Unit 5 MHz Typ. Max. Unit 0. ...
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... STOP condition setup time STOP condition hold time t SCKH t SCKL t SU:STA t HD:STA Data interface timing (I Revision 1.2 tDCH 100 tSCLH 500 tSCLL 500 tSU:STA 500 tHD:STA 500 tSU:STO 500 tHD:STO 500 t t DCSU DCH MTV212M64 (Rev. 1. HD:STO t SU:STO 2000/07/04 ...
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... SDIP Unit: mm Revision 1.2 2.540mm 1.778mm +/-0.127 0.254mm (min.) Symbol MTV212M64 (Rev. 1.2) 15.494mm +/-0.254 13.868mm +/-0.102 0.254mm +/-0.102 +/-3 16.256mm +/-0.508 Dimension in mm Min Nom Max 3.937 4.064 4 ...
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... TYP. 0.070 Package Type ROM Size (K) N: PDIP 64 S:SDIP V: PLCC Package Type ROM Size ( MTV212M64 (Rev. 1.2) 0.020 MIN. 0.013~0.021 TYP. 0.610 +/-0.02 0.500 0.010 0.070 USB Option Non-USB: N/A USB: U USB Option 2000/07/04 ...