MTV021 ETC-unknow, MTV021 Datasheet
MTV021
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MTV021 Summary of contents
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... This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product. GENERAL DESCRIPTION MTV021 is designed for monitor applications to display built-in characters or fonts onto monitor screens. The display operation occurs by transferring data and control information from the micro-controller to RAM through a serial data interface ...
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... Row 15, Column 26. 2/17 MTV021 VSSA 1 24 VSS VCO 2 23 ROUT GOUT VDDA BOUT 4 21 HFLB FBKG 5 20 SSB HTONE/PWMCK 6 19 MTV021N24 SDA VFLB 7 18 SCK VDD 8 17 PWM0 PWM7 9 16 PWM1 PWM6 10 15 PWM2 PWM5 11 14 PWM3 PWM4 12 13 MTV021 Revision 5.0 6/29/1999 2 C ...
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... While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission should be starting from pulling SSB to "low" level, enabling MTV021 to receiving mode, and retain "low" level until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1. ...
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... I C bus bus operation is only selected when SSB pin is left floating. And a valid transmission should be starting from writing the slave address 7AH, which is mask option, to MTV021. The protocol is shown in Figure 2. SCK SDA B7 START FIGURE 2. Data Transmission Protocol (I There are three transmission formats shown as below: ...
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... TABLE 2. Repeat line weight of character CH6 - CH0 Repeat Line Weight CH6,CH5=11 CH6,CH5=10 CH6,CH5=0x CH4 Input = b7, b6 Initiate 1, X ROW 1, X format (b) format (c) COL COL Where H = one horizontal line display time +18*3 +18*2 +18 +16 5/17 MTV021 format ( MTV021 Revision 5.0 6/29/1999 ...
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... VCLK Freq = HFLB Freq * HORR * 12 The VCLK frequency ranges from 6MHz to 96MHz selected by (VCO1, VCO0). In addition, when HFLB input is not present to MTV021, the PLL will generate a specific system clock, approximately 2.5MHz built-in oscillator to ensure data integrity. 3.6 Display & Row control registers The internal RAM contains display and row control registers ...
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... COLUMN WINDOW3 WINDOW4 FIGURE 4. Memory Map CRADDR BLINK CHS 7/17 MTV021 ROW E CTRL REG FRAME PWM D/A CRTL REG CRTL REG b0 LSB CWS MTV021 Revision 5.0 6/29/1999 ...
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... CWS - Define double width character to the respective row. 3.7 Character ROM MTV021 character ROM contains 272 built-in characters and symbols including 256 standard fonts and 16 multi-color fonts. The 256 standard fonts are located from address 0 to 255. And the 16 multi-color fonts are located from address 240 to 255 while CFONT bit is set to “ ...
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... And if the con ROW END ADDR LSB MSB LSB LSB VERTD HORD CH4 CH3 CH2 CH1 9/17 MTV021 LSB WEN - WSHD LSB b1 b0 LSB b1 b0 CH0 MTV021 Revision 5.0 6/29/1999 ...
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... Negative polarity FBKG output is selected. The initial value is 1 after power up HORR RSPACE MSB SHADOW FAN BLANK PWMCK SELVCL HSP 10/17 MTV021 b1 b0 LSB b1 b0 LSB WENCLR RAMCLR FBKGC VSP VCO1 VCO0 MTV021 Revision 5.0 6/29/1999 ...
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... Pixel rate < 17MHz = (0, 1) 17MHz < Pixel rate < 34MHz = (1, 0) 34MHz < Pixel rate < 68MHz = (1, 1) 68MHz < Pixel rate < 96MHz (vii)under or equal to 6.2K ohm: = (0, 0) 9.5MHz < Pixel rate < 19MHz = (0, 1) 19MHz < Pixel rate < 38MHz = (1, 0) 38MHz < Pixel rate < 76MHz 11/17 MTV021 Revision 5.0 6/29/1999 MTV021 ...
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... HFLB Freq * HORR * 12 / 256 HFLB Freq * HORR * 6 / 256 HFLB Freq * HORR * 3 / 256 HFLB Freq * HORR * 3 / 512 WSG WSB - WW31 WW30 WW21 WW20 ( 12/17 MTV021 CSR CSG CSB CFONT WW11 WW10 MTV021 Revision 5.0 6/29/1999 ...
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... In applications, all open-drain output pins should be pulled-up by external resistors to supply voltage (5V to 9V) for desired output range WH31 WH30 WH21 WH20 ( Horizontal lines M Pixels 13/17 MTV021 WH11 WH10 M Pixels N Horizontal lines WINDOW AREA Note: M and N are defined by the registers of row 15, column 21 and 22. MTV021 Revision 5.0 6/29/1999 ...
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... V -0.3 to VDD+0 -65 to +150 +70 C +4.75 to +5. +70 C Conditions (Notes 14/17 MTV021 b1 b0 LSB 0 1 255 Min. Max. 0.7 * VDD VDD+0.3 0.3 * VDD VSS-0.3 (0.2 * VDD for SSB pin) MTV021 Revision 5.0 6/29/1999 Units V V ...
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... SCKH t SCKL t BCSU t t DCSU DCH FIGURE 8. Data interface timing(SPI) 15/17 MTV021 Min. Max. VDD Typ. Max. Units - 130 KHz - BCH MTV021 Revision 5.0 6/29/1999 Units ...
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... Max 115 Min 100Ty 18 +/- p 2Typ t SCKH t SCKL t t DCSU DCH FIGURE 9. Data interface timing(I 312 +/-12 R40 250 +/-4 7 Typ 35 +/-5 15 Min 60 +/- 5Typ 16/17 MTV021 t HD:STO t SU:STO C) 2 R10Max ( +/-20 90 +/-20 350 +/- +/-4 55 +/-4 310Max MTV021 Revision 5.0 6/29/1999 ...
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... Myson Technology USA, Inc. 20111 Stevens Creek Blvd. #138 Cupertino, Ca. 95014, U.S.A. Tel:408-252-8788 17/17 MTV021 R10Max ( +/-20 90 +/-20 350 +/-20 250 +/- +/-4 55 +/-4 310Max R10Max (4X) 312+/-12 80+/-20 350+/-20 250+/-4 55+/-20 10 65+/-4 65+/-4 http://www.myson.com FAX: 408-252-8789 Sales@myson.com MTV021 Revision 5.0 6/29/1999 ...