ICM7232 Intersil Corporation, ICM7232 Datasheet - Page 8

• Manufacturer Part Number: ICM7232
• Description: Numeric/alphanumeric Triplexed Lcd Display Drivers
• Manufacturer: Intersil Corporation

MAXCMOS
Timing Diagrams
ICM7231 Family Description
The ICM7231 drives displays with 8 seven-segment digits with
two independent annunciators per digit, accepting six data
bits and three digit address bits from parallel inputs controlled
by a chip select input. The data bits are subdivided into four
binary code bits and two annunciator control bits.
The ICM7232 drives 10 seven-segment digits with two inde-
pendent annunciators per digit. To write into the display, six
bits of data and four bits of digit address are clocked serially
into a shift register, then decoded and written to the display.
Input levels are TTL compatible, and the DATA ACCEPTED
output on the serial input devices will drive one LSTTL load.
The intermediate voltage levels necessary to drive the dis-
play properly are generated by an on-chip resistor string,
and the output of a totally self-contained on-chip oscillator is
used to generate all display timing. All devices in this family
have been fabricated using Intersil’ MAXCMOS
and all inputs are protected against static discharge.
Triplexed (
Figure 4 shows the connection diagram for a typical
7-segment display with two annunciators such as would be
used with an ICM7231 or ICM7232 numeric display driver.
Figure 5 shows the voltage waveforms of the common lines
ACCEPTED
OUTPUT
CLOCK
WRITE
INPUT
INPUT
INPUT
DATA
DATA
DATA
is a registered trademark of Intersil Corporation.
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1
t
WLL
/
3
Multiplexed) Liquid Crystal Displays
t
CI
ENTER
FIRST
AN1
t
DS
FIGURE 3. ICM7232 INPUT TIMING DIAGRAM, LEAVING BOTH ANNUNCIATORS OFF
t
WP
1
RESETS SHIFT REGISTER
AND INPUT CONTROL
LOGIC WHEN DATA
ACCEPTED HIGH
VALID
DATA
BD0
AN2
xxxxx
xxxxx
xxxxx
xxxxx
t
BD0
DH
2
VALID
DATA
BD1
t
CI
xxxxx
xxxxx
xxxxx
xxxxx
BD1
ICM7231, ICM7232
ICM7232 WRITE ORDER
process
BD2
3
VALID
DATA
BD2
DO NOT CARE
9-26
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and one segment line, chosen for this example to be the “a,
g, d” segment line. This line intersects with BP1 to form the
“a” segment, BP2 to form the “g” segment and BP3 to form
the “d” segment. Figure 5 also shows the waveform of the “a,
g, d” segment line for four different ON/OFF combinations of
the “a”, “g” and “d” segments. Each intersection (segment or
annunciator) acts as a capacitance from segment line to
common line, shown schematically in Figure 6. Figure 7
shows the voltage across the “g” segment for the same four
combinations of ON/OFF segments used in Figure 5.
SEGMENT LINE CONNECTIONS
BD3
FIGURE 4. CONNECTION DIAGRAMS FOR TYPICAL
an
2
SEGMENT LINES
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e
f
A0
7
VALID
DATA
d
7-SEGMENT DISPLAYS
A2
g
a
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xxxxxxx
c
b
an
A1
1
t
t
CWS
ODI
BP1
BP2
BP3
8
VALID
DATA
A2
A3
an
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BACKPLANE CONNECTIONS
t
WP
2
t
ODH
DECODES AND STORES
DATA, RESETS SHIFT
REGISTER AND LOGIC
WHEN DATA ACCEPTED
IS LOW
ENTER
LAST
A3
e
f
d
g
a
c
b
an
1