ADRF6601 Analog Devices, Inc., ADRF6601 Datasheet - Page 17

• Manufacturer Part Number: ADRF6601
• Description: 750 Mhz To 1160 Mhz Rx Mixer With Integrated Fractional-n Pll And Vco
• Manufacturer: Analog Devices, Inc.

APPLICATIONS INFORMATION
BASIC CONNECTIONS FOR OPERATION
Figure 21 shows the basic connections for the ADRF6601. The
six power supply pins should be individually decoupled using
100 pF and 0.1 μF capacitors located as close as possible to the
device. In addition, the internal decoupling nodes (DECL3P3,
DECL2P5, and DECLVCO) should be decoupled with the
capacitor values shown in Figure 21.
The RF input is internally ac-coupled and needs no external
bias. The IF outputs are open collector, and a bias inductor
is required from these outputs to VCC.
A peak-to-peak differential swing on RF
for a sine wave input) results in an IF output power of 4.7 dBm.
The reference frequency for the PLL should be from 12 MHz
to 160 MHz and should be applied to the REF_IN pin, which
should be ac-coupled and terminated with a 50 Ω resistor, as
OPEN
LO IN/OUT
(0402)
S1
VCC1
RED
R56
REFOUT
0Ω
REFIN
R55
OPEN
(0402)
TC1-1-13+
(0402)
49.9Ω
4
5
R70
T8
(0402)
R16
0Ω
3
1
(0402)
C31
1nF
LODRV_EN
(0402)
(0402)
1nF
1nF
C5
C6
MUXOUT
REF_IN
LON
LOP
36
37
38
6
8
VCC_LO
ADRF6601
VCC
RED
+5V
÷2
÷4
×2
34
R6
0Ω
(0402)
VCC_V2I
C7
0.1µF
(0402)
C8
100pF
(0402)
MUX
4
IN
27
7
R26
0Ω
(0402)
FRACTION
SENSOR
VCC_MIX
of 1 V (0.353 V rms
11
TEMP
INTERPOLATOR
C25
0.1µF
(0402)
C24
100pF
(0402)
REG
THIRD-ORDER
Figure 21. Basic Connections for Operation of the ADRF6601
FRACTIONAL
15
20
22
21
(ORANGE)
R25
0Ω
(0402)
MODULUS
VCC_LO
23
C23
0.1µF
(0402)
C22
100pF
(0402)
–
+
POINT
TEST
24
FREQUENCY
DETECTOR
CP
PHASE
25
N COUNTER
17
21 TO 123
28
R24
0Ω
(0402)
(0603)
INTEGER
(0402)
22pF
(0603)
R38
30
C14
0Ω
10µF
C20
0.1µF
(0402)
C21
100pF
(0402)
REG
C43
VCC2
Rev. 0 | Page 17 of 24
31
(0402)
35
R37
10
0Ω
R11
OPEN
(0402)
OPEN
(0402)
R17
0Ω
(0402)
R9 10kΩ
PRESCALER
(0402)
CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
OPEN
(0402)
C2
R
R10
3.0kΩ
(0603)
C19
0.1µF
(0402)
C18
100pF
(0402)
C15
2.7nF
(1206)
SET
S2
VCC1
R2
VCC
÷2
(0402)
5
R1
0Ω
R54
10kΩ
(0402)
100pF
(0402)
1
R65 10kΩ
C13
6.8pF
(0603)
R7
0Ω
(0402)
(0402)
BUFFER
C1
shown in Figure 21. The reference signal, or a divided-down
version of the reference signal, can be brought back off chip at
the multiplexer output pin (MUXOUT). A lock detect signal
and a voltage proportional to the ambient temperature can also
be selected on the multiplexer output pin.
The loop filter is connected between the CP and VTUNE pins.
When connected in this way, the internal VCO is operational.
For information about the loop filter components, see the
Evaluation Board Configuration Options section.
Operation with an external VCO is also possible. In this case,
the loop filter components should be referred to ground. The
output of the loop filter is connected to the input voltage pin of
the external VCO. The output of the VCO is brought back into
the device on the LOP and LON pins, using a balun if necessary.
BUFFER
(0402)
C9
0.1µF
(0402)
C10
100pF
(0402)
10kΩ
R53
(0402)
R12
0Ω
(0402)
R20
C40
22pF
(0603)
0Ω
3
CP
MUX
2:1
(0402)
CORE
VCO
39
R19
0Ω
VTUNE
1
DIVIDER
R62
0Ω
(0402)
4, 2, 1
2
÷2
DIV
BY
3
40
R35
0Ω
(0402)
DECLVCO
OPEN
(0402)
4
R63
5
VTUNE
6
R30
0Ω
(0402)
16
INTERFACE
7
IFP
13 12
SPI
8
18
R57
0Ω
(0402)
VCC
+5V
9
19
14
IFN
P1
9-PIN
DSUB
R36
0Ω
(0402)
26
29
9
2
(0402)
C29
0.1µF
(0402)
R59
DECL2P5
DECL3P3
RF
IP3SET
0Ω
C34
OPEN
(0402)
C33
OPEN
(0402)
C32
OPEN
(0402)
IN
C16
100pF
(0402)
C12
100pF
(0402)
1
2
3
(0402)
R28
(0402)
0Ω
R27
4
R52
OPEN
(0402)
R51
OPEN
(0402)
R50
OPEN
(0402)
0Ω
5
(0402)
(0402)
(0402)
R18
R43
0Ω
R8
0Ω
0Ω
RFIN
C27
0.1µF
(0402)
ADRF6601
RFOUT
C17
0.1µF
(0402)
C11
0.1µF
(0402)
C42
10µF
(0603)
C41
OPEN
(0603)