ADN2815 Analog Devices, Inc., ADN2815 Datasheet - Page 18

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ADN2815

Manufacturer Part Number
ADN2815
Description
Continuous Rate 10 Mb/s To 1.25 Gb/s Clock And Data Recovery Ic
Manufacturer
Analog Devices, Inc.
Datasheet
ADN2815
Additional Features Available via the I
Coarse Data Rate Readback
The data rate can be read back over the I
approximately ±10% without the need of an external reference
clock. A 9-bit register, COARSE_RD[8:0], can be read back
when LOL is deasserted. The eight MSBs of this register are the
contents of the RATE[7:0] register. The LSB of the
COARSE_RD register is Bit MISC[0].
Table 13 provides coarse data rate readback to within ±10%.
2
C interface to
2
C Interface
Rev. 0 | Page 18 of 24
System Reset
A frequency acquisition can be initiated by writing a 1 followed
by a 0 to the I
frequency acquisition while keeping the ADN2815 in the
operating mode that it was previously programmed to in
Registers CTRL[A], CTRL[B], and CTRL[C].
2
C Register Bit CTRLB[5]. This initiates a new

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